overriding parameters

[jan.kindt@gmail.com]

Hi,

I've got a Testbench and design that looks more or less like the
following :
TB_case1.vhd
--- TB.vhd
--- Gatelevelnetlist.v
--- EEPROMVector.v
--- EEPROMVector.v
--- Ram.v

in the file EEPROMVector0.v, there is a param definition : param
PreloadVectorFile="vector.hex";
in the file RAM.v, there is an likewise param : param
InitRamFile="ram.hex";

Since I have two instantiations of the EEPROMVector in the gatelevel
netlist (called Vector0 and Vector1), I want to override the
parameter. I do not want to override using defparam in the gatelevel
netlist as this would force me to re-edit the netlist each time there
is a new netlist delivered. How can I do this ?
Likewise, how can I change the Ram initialisation parameter ?

I tried two things :
1. NCELAB lib_sim.TBE_TB_case1:TBA_TB_case1 +defparam
TBE_TB_case1.TB_inst.Gatelevelnetlist_inst.Vector0.PreloadVectorFile="Vector0.hex" ...and
so on
NCELAB complains about not finding the thing in the libraries
2. I created a file ParamOverrides.v with the same defparams in it.
compiled it and added the file to the elaborator... about the same
error about not finding it in the hierarchy : Hierarchical name
component lookup failed

can someone explain me how to do it right ?

 

[gabor]

On Aug 31, 4:55 am, "jan.ki...@gmail.com" <jan.ki...@gmail.com> wrote:

Hi,

I've got a Testbench and design that looks more or less like the
following :
TB_case1.vhd
--- TB.vhd
--- Gatelevelnetlist.v
--- EEPROMVector.v
--- EEPROMVector.v
--- Ram.v

in the file EEPROMVector0.v, there is a param definition : param
PreloadVectorFile="vector.hex";
in the file RAM.v, there is an likewise param : param
InitRamFile="ram.hex";

Since I have two instantiations of the EEPROMVector in the gatelevel
netlist (called Vector0 and Vector1), I want to override the
parameter. I do not want to override using defparam in the gatelevel
netlist as this would force me to re-edit the netlist each time there
is a new netlist delivered. How can I do this ?
Likewise, how can I change the Ram initialisation parameter ?

I tried two things :
1. NCELAB lib_sim.TBE_TB_case1:TBA_TB_case1 +defparam
TBE_TB_case1.TB_inst.Gatelevelnetlist_inst.Vector0.PreloadVectorFile="Vector0.hex" ...and
so on
NCELAB complains about not finding the thing in the libraries
2. I created a file ParamOverrides.v with the same defparams in it.
compiled it and added the file to the elaborator... about the same
error about not finding it in the hierarchy : Hierarchical name
component lookup failed

can someone explain me how to do it right ?

If I had this scenario, I'd add a verilog wrapper around
Gatelevelnetlist.v with the defparams for the two EEPROMVector
instantiations, and another verilog wrapper around Ram.v
with more defparams. Module port lists for the wrappers
would exactly match the wrapped module port lists to
minimize changes to the testbench. It's too bad you
can't just place the defparams in the VHDL testbench...

 

[jan.kindt@gmail.com]

gabor wrote:

On Aug 31, 4:55 am, "jan.ki...@gmail.com" <jan.ki...@gmail.com> wrote:
Hi,

I've got a Testbench and design that looks more or less like the
following :
TB_case1.vhd
--- TB.vhd
--- Gatelevelnetlist.v
--- EEPROMVector.v
--- EEPROMVector.v
--- Ram.v

in the file EEPROMVector0.v, there is a param definition : param
PreloadVectorFile="vector.hex";
in the file RAM.v, there is an likewise param : param
InitRamFile="ram.hex";

Since I have two instantiations of the EEPROMVector in the gatelevel
netlist (called Vector0 and Vector1), I want to override the
parameter. I do not want to override using defparam in the gatelevel
netlist as this would force me to re-edit the netlist each time there
is a new netlist delivered. How can I do this ?
Likewise, how can I change the Ram initialisation parameter ?

I tried two things :
1. NCELAB lib_sim.TBE_TB_case1:TBA_TB_case1 +defparam
TBE_TB_case1.TB_inst.Gatelevelnetlist_inst.Vector0.PreloadVectorFile="Vector0.hex" ...and
so on
NCELAB complains about not finding the thing in the libraries
2. I created a file ParamOverrides.v with the same defparams in it.
compiled it and added the file to the elaborator... about the same
error about not finding it in the hierarchy : Hierarchical name
component lookup failed

can someone explain me how to do it right ?


If I had this scenario, I'd add a verilog wrapper around
Gatelevelnetlist.v with the defparams for the two EEPROMVector
instantiations, and another verilog wrapper around Ram.v
with more defparams. Module port lists for the wrappers
would exactly match the wrapped module port lists to
minimize changes to the testbench. It's too bad you
can't just place the defparams in the VHDL testbench...

Thats's a possibility. But it requires modifying the module where the
verilog is instantiated. Since the same testbench works for RTL level
(there are defparams in the verilog module which instantiates
EEPROMVector.v, but they got synthesized away), I would rather not
touch the testbench..