overflow problem

[Zaki]

Hello,

Im a beginner with VHDL and there's a big problem.
I want to realize an ALU with signed and unsigned addition and subtraction.
The problem is the overflow:

I tried to realize the overflow that way:

--ADD
WHEN "0101" =>
signedResult := conv_signed(conv_integer(signed(a))

+conv_integer(signed(b)),8);
c <= conv_std_logic_vector(signedResult,8);

--overflow
if(conv_integer(signedResult) >= conv_signed(128,8) or
conv_integer(signedResult) < conv_signed(-128,32)) then

overflow <= '1';
else
overflow <= '0';
end if;


The overflow-signal is always '1'.
I dont know why this won't work....

Thx