output using as input.

[Jack]

Hi ~
I have some question about assign.

ex)

output a;
output b;
output c;

reg a;
reg b;
reg [2:0] count;
wire c;

assign c = (a || b) ? count + 1 : 0

Here, a and b was used to input.
I think that it's not good. but some other people said that good.
I don't know that it's is right or wrong ?

 

[Muzaffer Kal]

On Mon, 5 May 2008 08:18:46 -0700 (PDT), Jack <love.theme@gmail.com>
wrote:

Hi ~
I have some question about assign.

ex)

output a;
output b;
output c;

reg a;
reg b;
reg [2:0] count;
wire c;

assign c = (a || b) ? count + 1 : 0

Here, a and b was used to input.
I think that it's not good. but some other people said that good.
I don't know that it's is right or wrong ?

It's certainly valid verilog so it's "right" but as to goodness it can
be debated. Because 'c' is not a registered output timing of the path
which uses it would need to be shared between this module and the
consumer of 'c'. Some flows don't like that too much but in today's
world of RTL to GDS in a single tool/run, it may not matter.

 

[glen herrmannsfeldt]

Jack wrote:

I have some question about assign.

output a;
output b;
output c;

reg a;
reg b;
reg [2:0] count;
wire c;

assign c = (a || b) ? count + 1 : 0

Here, a and b was used to input.
I think that it's not good. but some other people said that good.
I don't know that it's is right or wrong ?

Post a complete module, otherwise it is hard to say.

You can use outputs in other expressions, but they should be
assigned somewhere.

-- glen