output = clock

[Ponkan]

Hi All,

I have a design running with a general clock 'clk' and one of my
outputs is exactly 'clk' enabled by an internal signal ('enable').
Whenever 'enable' is actived output = 'clk'. On the other hand, if
'enable' is not actived, output = 0.
A very naive and dangerous way to do this is simply using a AND gate
but glitches can occur and I don't want that. Multiplying 'clk' by 2
and using a FF with clock enable could work but it is not always easy
to do that (depends on the device). Does any of you have any good idea
to implement this thing?

 

[John_H]

"Ponkan" <amizadefriend131@hotmail.com> wrote in message
news:28c5c943.0309240449.79fd189@posting.google.com...

Hi All,

I have a design running with a general clock 'clk' and one of my
outputs is exactly 'clk' enabled by an internal signal ('enable').
Whenever 'enable' is actived output = 'clk'. On the other hand, if
'enable' is not actived, output = 0.
A very naive and dangerous way to do this is simply using a AND gate
but glitches can occur and I don't want that. Multiplying 'clk' by 2
and using a FF with clock enable could work but it is not always easy
to do that (depends on the device). Does any of you have any good idea
to implement this thing?

If you want the clock to be low when disabled, register your enable on the
falling edge of the clock. As long as the clk-to-out plus propagation delay
of the enable to the AND gate is less than 1/2 cycle, you will always avoid
glitches.

Alternatively, register on the rising edge and OR the clock with the disable
signal resulting in a steady high state when disabled. Same timing issues
apply.

 

[Sajan]

Hi
I would suggest you use a clock buffer with enable. It should be
available in the library you are using. Check for it,
The equivalent circuit will be something like this.

LATCH
_________
| |
G------| |_______
| | |
| | | AND
clk -----o| | | ____
| |_________| | | >
| |___| >___________ X
|_________________________| >
|____>

These clock buffer libraries provided in the libraries are glitch
resistant.
Hope this could be of help.

Regards,
Sajan.


"John_H" <johnhandwork@mail.com> wrote in message news:<E1jcb.8$Cr.7178@news-west.eli.net>...

"Ponkan" <amizadefriend131@hotmail.com> wrote in message
news:28c5c943.0309240449.79fd189@posting.google.com...
Hi All,

I have a design running with a general clock 'clk' and one of my
outputs is exactly 'clk' enabled by an internal signal ('enable').
Whenever 'enable' is actived output = 'clk'. On the other hand, if
'enable' is not actived, output = 0.
A very naive and dangerous way to do this is simply using a AND gate
but glitches can occur and I don't want that. Multiplying 'clk' by 2
and using a FF with clock enable could work but it is not always easy
to do that (depends on the device). Does any of you have any good idea
to implement this thing?

If you want the clock to be low when disabled, register your enable on the
falling edge of the clock. As long as the clk-to-out plus propagation delay
of the enable to the AND gate is less than 1/2 cycle, you will always avoid
glitches.

Alternatively, register on the rising edge and OR the clock with the disable
signal resulting in a steady high state when disabled. Same timing issues
apply.