Out of memory error in Synplicity

[kb33]

Hi,

I am trying to synthesize my design (it has FSM and for loops inside
the FSM) using SYnplicity. The target FPGA is Xilinx Virtex 2 XC2V6000.
After about 45 minutes of running the synthesis on the top level
design, the tool gives an error of "out of memory" for one of the
embedded modules. Any suggestions on why I get this error, and are
there any compilation options which can be set to prevent this error?

Thanks
kb33

 

[Ajeetha]

Without actual code and the tool it is hard to comment. Few thoughts:

--> For loops may cause such problems depending on their bounds - try
reducing the for range (say make it for 0..3) - I know this will change
functionality, but to isolate the problem this trick can help.

--> Contact their support desk.
--> Switch to their latest/best version (ask the support which is
"best" version)

HTH
Ajeetha, CVC
www.noveldv.com

kb33 wrote:

Hi,

I am trying to synthesize my design (it has FSM and for loops inside
the FSM) using SYnplicity. The target FPGA is Xilinx Virtex 2 XC2V6000.
After about 45 minutes of running the synthesis on the top level
design, the tool gives an error of "out of memory" for one of the
embedded modules. Any suggestions on why I get this error, and are
there any compilation options which can be set to prevent this error?

Thanks
kb33

 

[kb33]

Hi,

I am inserting the piece of code which is generating the "out of
memory" error. All variable are defined as registers. The Synplicity
tool is giving this error at the line - "disable Loop_oldconn". D_FUNC
is one of the states of the State Machine in the code

Thanks

`D_FUNC:
if (~values_rdy_n) //Condition 1:
Are all values available?
if (v_bit_array[index_val]) //Condition 2: Does location have a
valid entry?
begin: Loop_oldconn //Scan through part of
memory to find a matching connection
for (cntr_comb=0; cntr_comb < `MAX_CONN; cntr_comb =
cntr_comb + 1)
begin
if((connect_array[val_array[cntr_comb]] == temp_state1)
|| (connect_array[val_array[cntr_comb]] == temp_state2))
begin
next_state <= `UPDATE_CONN;
disable Loop_oldconn;
end
end
next_state <= `CHK_NEWCONN;
cntr_comb <= 0;
end // block: Loop_oldconn

else //Condition 2
false, it's a new connection
begin
next_state <= `NEW_CONN;
cntr_comb <= 0;
end // else: !if(v_bit_array[index_val])

else //Condition 1
false; waiting for values_rdy_n signal
begin
next_state <= `D_FUNC;
cntr_comb <= 0;
end

 

[Ajeetha]

Why do use disable? Some time back disable was not allowed by many
synthesis tools. Why not simply implement it using a single bit reg -
that might solve the problem.

Regards
Ajeetha, CVC
www.noveldv.com

kb33 wrote:

Hi,

I am inserting the piece of code which is generating the "out of
memory" error. All variable are defined as registers. The Synplicity
tool is giving this error at the line - "disable Loop_oldconn". D_FUNC
is one of the states of the State Machine in the code

Thanks

`D_FUNC:
if (~values_rdy_n) //Condition 1:
Are all values available?
if (v_bit_array[index_val]) //Condition 2: Does location have a
valid entry?
begin: Loop_oldconn //Scan through part of
memory to find a matching connection
for (cntr_comb=0; cntr_comb < `MAX_CONN; cntr_comb =
cntr_comb + 1)
begin
if((connect_array[val_array[cntr_comb]] == temp_state1)
|| (connect_array[val_array[cntr_comb]] == temp_state2))
begin
next_state <= `UPDATE_CONN;
disable Loop_oldconn;
end
end
next_state <= `CHK_NEWCONN;
cntr_comb <= 0;
end // block: Loop_oldconn

else //Condition 2
false, it's a new connection
begin
next_state <= `NEW_CONN;
cntr_comb <= 0;
end // else: !if(v_bit_array[index_val])

else //Condition 1
false; waiting for values_rdy_n signal
begin
next_state <= `D_FUNC;
cntr_comb <= 0;
end

 

[kb33]

The thing is that I am running the FOR loop in one clock cycle. If I
use a register bit to exit out of the loop, the register will get the
appropriate value only in the next clock cycle (I use separate blocks
for combinational anf sequential logic, and am using only non-blocking
statements). Hence I am not sure how that would help me exit from the
loop. Also, I have synthesized the "disable" statement in the past, so
I am assuming that it is possible to do so using the Synplicity tool.
Please comment.

Thanks
Kanchan

 

[Stephen Williams]

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kb33 wrote:

begin: Loop_oldconn
for (cntr_comb=0; cntr_comb < `MAX_CONN; cntr_comb =cntr_comb + 1)
begin
if((connect_array[val_array[cntr_comb]] == temp_state1)
|| (connect_array[val_array[cntr_comb]] == temp_state2))
begin
next_state <= `UPDATE_CONN;
disable Loop_oldconn;
end
end

Well, I can't say I know how Synplicity works, but I have written
synthesizers and this loop concerns me. Consider that a synthesizer
will unroll this loop. It must. There is no other way to generate
gates for this sort of thing. So the compiler needs to figure out
at compile time exactly how many iterations there will be, and will
generate all the iterations in parallel. So that "disable" is doing
nothing for you, and may in fact be confusing the tool.

Some common advice I've heard on this list: Ask yourself "what
kind of hardware do I expect from this?" So what sort of gate or
logic do you expect to come from that "disable" statement?

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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[Rob Dekker]

"kb33" <kanchan.devarakonda@gmail.com> wrote in message news:1164350425.978847.72300@h54g2000cwb.googlegroups.com...
[...]

begin: Loop_oldconn //Scan through part of
memory to find a matching connection
for (cntr_comb=0; cntr_comb < `MAX_CONN; cntr_comb =
cntr_comb + 1)
begin
if((connect_array[val_array[cntr_comb]] == temp_state1)
|| (connect_array[val_array[cntr_comb]] == temp_state2))
begin
next_state <= `UPDATE_CONN;
disable Loop_oldconn;
end
end
next_state <= `CHK_NEWCONN;
cntr_comb <= 0;
end // block: Loop_oldconn

This is a nasty loop to synthesize.

"connect_array[val_array[cntr_comb]]" requires a big multi-bit multiplexor, and you need MAX_CONN of these.
That is a lot of work (logic) to be done in one clock cycle.

How big is MAX_CONN ? How big is 'val_array' ? And how big is 'connect_array' ?
Depending on these sizes, the circuit could easily blow up.

Where is the program when it runs out of memory ?
Is it still reading / compiling the design, or is it in 'optimization' phase ?

One tip :
Take away the 'disable' statement. It does not hurt the function if you remove it (since the only thing that can happen is that
next_state goes to CHK_NEWCONN,
and disable statements can quite easily generate a lot of aditional logic initially, which then would need to be optimized away.

Another tip :
Assign "connect_array[val_array[cntr_comb]] " to a temporary variable before you test against 'temp_state1' and 'temp_state2'.
That can possibly save you half he initial logic (depending on how quickly the synrhesis tool finds out that there are two big
common subexpressions).

else //Condition 2
false, it's a new connection
begin
next_state <= `NEW_CONN;
cntr_comb <= 0;
end // else: !if(v_bit_array[index_val])

else //Condition 1
false; waiting for values_rdy_n signal
begin
next_state <= `D_FUNC;
cntr_comb <= 0;
end