others in state machine

[Jerker Hammarberg (DST)]

Hello! I have noticed that if I add a "when others" branch in a state
machine case statement, the resulting FPGA becomes considerably smaller. To
be clear,

type state_type is (s0, s1);
signal state: state_type;
....
process(clk, rst)
begin
if (rst = '1') then
state <= s0;
elsif clk'event and clk = '1' then
case state of
when s0 =>
-- do something
state <= s1;
when s1 =>
-- do something else
state <= s0;
when others =>
state <= s0;
end case;
end if;
end process;

is smaller than if I remove the "when others" branch. What's the reason? My
second question is how this branch can be reached in the FPGA? It happens to
me. I understand that it can be reached during simulation if "state" is not
initialized, but how can it happen in reality?

I use Xilinx XST with FSM encoding set to "auto".

Thanks in advance for any help!

/Jerker

 

[Tim Hubberstey]

"Jerker Hammarberg (DST)" wrote:

Hello! I have noticed that if I add a "when others" branch in a state
machine case statement, the resulting FPGA becomes considerably smaller. To
be clear,

type state_type is (s0, s1);
signal state: state_type;
...
process(clk, rst)
begin
if (rst = '1') then
state <= s0;
elsif clk'event and clk = '1' then
case state of
when s0 =
-- do something
state <= s1;
when s1 =
-- do something else
state <= s0;
when others =
state <= s0;
end case;
end if;
end process;

is smaller than if I remove the "when others" branch. What's the reason? My
second question is how this branch can be reached in the FPGA? It happens to
me. I understand that it can be reached during simulation if "state" is not
initialized, but how can it happen in reality?

I use Xilinx XST with FSM encoding set to "auto".

Actually, the "when others" is unreachable in simulation since you are
using enumerated types and have included all possible values.

It should also be unreachable in an FPGA unless the synthesizer decides
to use some form of encoding that has possible illegal states in the
state register. For a 2-state machine like you've shown, it only needs
to have a 1-bit state register and so there should be no illegal states.
It's possible that with the "when others" the tool decides to use binary
encoding and without it uses one-hot encoding (I'm guessing here). FPGA
synthesizers like one-hot encoding (it maps better to FPGA
architectures), so it is always a good idea to include a "when others"
state to reset the machine to something sane in case the state vector
gets trashed by something (noise, gremlins, etc.).
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Jerker Hammarberg (DST)]

It should also be unreachable in an FPGA unless the synthesizer decides
to use some form of encoding that has possible illegal states in the
state register. For a 2-state machine like you've shown, it only needs
to have a 1-bit state register and so there should be no illegal states.
It's possible that with the "when others" the tool decides to use binary
encoding and without it uses one-hot encoding (I'm guessing here). FPGA
synthesizers like one-hot encoding (it maps better to FPGA
architectures), so it is always a good idea to include a "when others"
state to reset the machine to something sane in case the state vector
gets trashed by something (noise, gremlins, etc.).

That makes sense, thanks a lot! You're right, the actual state machine where
it happens has more states. I suppose you mean that with "when others" it
uses one-hot encoding and without it it uses binary encoding.

/Jerker

 

[Mike Treseler]

Tim Hubberstey wrote:

so it is always a good idea to include a "when others"
state to reset the machine to something sane in case the state vector
gets trashed by something (noise, gremlins, etc.).

The when others clause also provides some protection
in case the type state_type is ever edited.

-- Mike Treseler