Or'ing output from conditionally generated instances

[Brandon]

I have a set of generated instances and I'd like to OR all their ports
of type std_logic. The structures are generated according to a
parameter, so I can't manually write out the logic equation, which
would be quite tedious anyways. How could I go about doing this?

I think that it's probably possible to use a for loop and do an OR
accumulation. I've compiled the following successfully:

<SNIP>
architecture rtl_ar of myentity is
-- array of std_logic:
signal mac_douten : ARRAYOFSTDL_T(CONSTANT_C downto 0);
..
..
..
comb_proc: process (...,mac_douten)
variable douten_oraccum : std_logic;

begin
.
.
.

-- OR dout_en outputs from each MAC
douten_oraccum := '0';
for index in 0 to mac_douten'length(1)-1 loop
douten_oraccum := douten_oraccum or mac_douten(index);
end loop;
douten_reg_d <= douten_oraccum;
.
.
.
end process comb_proc;
end rtl_ar;

</SNIP>

Should this work? Will this force the synthesizer to create cascaded
logic, because I'd rather it not.

Thanks,
-Brandon