ORing of the 2 bit vector with 1 bit

[rajan]

Hi,

I want to "OR" a 2-bit signal with a 1-bit signal in VHDL. I appreciate your help.

regards,
rajan

 

[dutchgoldtony]

result <= twoBit(0) OR twoBit(1) OR bit;

 

[Ralf Hildebrandt]

rajan wrote:

I want to "OR" a 2-bit signal with a 1-bit signal in VHDL. I appreciate your help.

Did you spend at least one minute to think about it?


signal twobits : std_ulogic_vector(1 downto 0);
signal onebit : std_ulogic;
signal result1 : std_ulogic_vector(1 downto 0);
signal result2 : std_ulogic_vector(1 downto 0);


result1(0) <= onebit OR twobits(0);
result1(1) <= onebit OR twobits(1);


process(onebit, twobits)
begin
for N in twobits'low to twobits'high loop
result2(N) <= twobits(N) OR onebit;
end loop;
end process;


Solution 2 is extensible for wider word widths.


So, now tell me, where was you problem? Maybe you should study a VHDL book before starting
to try to do something with VHDL.

Ralf