orcad 9.1 express

[morosh]

Hello:
I'm newbie to Orcad 9.1 express, I'd like to synthesize a gal22v10 with
a simple vhdl file just to test,
I wrote the following file:

library ieee;

use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use WORK.mylib1.all;

entity cmp_bdt is
port(
CLOCK : in std_logic;
RESET : in std_logic;
CK1 : out std_logic;
CK2 : out std_logic;
CK3 : out std_logic);
end cmp_bdt;

architecture arch_behavioral of cmp_bdt is
-- Component declarations
-- Signal declarations
signal cpt : std_logic_vector(2 downto 0);
begin

GEN_CPT: process(CLOCK,RESET)
begin
if (CLOCK'event and CLOCK='1') then
if (RESET='1') then
CPT <= "000";
else
CPT <= CPT + 1;
end if;
end if;
end process;

CK1 <= cpt(0);
CK2 <= cpt(1);
CK3 <= cpt(2);


end arch_behavioral;



I tried to build, I get errors and the following report:

************************************************************************
OrCAD Simple PLD Fitter tools
************************************************************************


OrCAD PLD FITTER x1.11 11/5/98 (Source file
e:\My_data\dev\vhdl\orcad\gal22v10\Timed\gal22v10.jed
)
Copyright (C) 1988-1998 OrCAD All Rights Reserved.

1. Parsing input file



2. Loading device tables

3. Converting pin connections

4. Expanding source statements
Signal EXP_N532
Signal EXP_N535
Signal EXP_N531
Signal EXP_N534
Signal EXP_N530
Signal EXP_N533
Signal EXP_N528
Signal EXP_N515
Signal EXP_N523
Signal EXP_N529
Signal EXP_N526
Signal EXP_N524
Signal EXP_N527
Signal EXP_N525
Signal EXP_N514
Signal EXP_N518
Signal EXP_N517
Signal EXP_N522
Signal EXP_N520
Signal EXP_N521
Signal EXP_N519
Signal EXP_N513
Signal EXP_N146
Signal EXP_N143
Signal EXP_N140
Signal EXP_N131
Signal EXP_N130
Signal EXP_N129
Signal CK1
Signal CK2
Signal CK3
Signal EXP_N512
Signal EXP_N137
Signal EXP_N135
Signal EXP_N133

5. Reducing equations
Signal CK1
Signal CK2
Signal CK3
Signal EXP_N137
Signal EXP_N135
Signal EXP_N133

6. Configuring architectural fuses
ERROR (PLD2763) Signal RESET is not input to the array.
ERROR (PLD2763) Signal CLOCK is not input to the array.

7. Generating fuse array
WARNING (PLD1364) Signal CK1 is not output from the array.
WARNING (PLD1364) Signal CK2 is not output from the array.
WARNING (PLD1364) Signal CK3 is not output from the array.
ERROR (PLD2766) Signal EXP_N137 does not have a valid clock portion.
ERROR (PLD2765) Signal EXP_N137 has too many product terms.
ERROR (PLD2766) Signal EXP_N135 does not have a valid clock portion.
ERROR (PLD2765) Signal EXP_N135 has too many product terms.
ERROR (PLD2766) Signal EXP_N133 does not have a valid clock portion.
ERROR (PLD2765) Signal EXP_N133 has too many product terms.

8. Checking for error conditions

NOTE (PLD0200) Eight fatal errors found in input file.
NOTE (PLD0201) Three warnings.


9. Writing language file

NOTE (PLD0202) 2/19/6 6:52 pm (Sunday)
NOTE (PLD0204) Elapsed time 6 seconds

Adding files to PM:
Adding e:\My_data\dev\vhdl\orcad\gal22v10\Timed\GAL22V10.LST
Adding e:\My_data\dev\vhdl\orcad\gal22v10\Timed\GAL22V10.VHD


Can someone help? I like to know also how to assign in/out signals to
pins?

Thanks

Morosh (gvnl@yahoo.fr)

 

[Joseph2k]

morosh wrote:

Hello:
I'm newbie to Orcad 9.1 express, I'd like to synthesize a gal22v10 with
a simple vhdl file just to test,
I wrote the following file:

library ieee;

use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use WORK.mylib1.all;

<huge snip>

Thanks

Morosh (gvnl@yahoo.fr)

Well "doh"! Orcad is a reasonably good analog schematic capture tool, but

it is not a front end to VHDL or Verilog; they have their own front ends.
--
JosephKK
Gegen dummheit kampfen Die Gotter Selbst, vergebens.
--Shiller

 

[Charlie Edmondson]

Joseph2k wrote:

morosh wrote:


Hello:
I'm newbie to Orcad 9.1 express, I'd like to synthesize a gal22v10 with
a simple vhdl file just to test,
I wrote the following file:

library ieee;

use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use WORK.mylib1.all;



huge snip

Thanks

Morosh (gvnl@yahoo.fr)


Well "doh"! Orcad is a reasonably good analog schematic capture tool, but
it is not a front end to VHDL or Verilog; they have their own front ends.
Actually, no. Orcad Express was a VHDL tool, that used Capture as its

front end, and not too bad a one at that. It was lost after the
purchase by Cadence.

Charlie

 

[Joseph2k]

Charlie Edmondson wrote:

Joseph2k wrote:
morosh wrote:


Hello:
I'm newbie to Orcad 9.1 express, I'd like to synthesize a gal22v10 with
a simple vhdl file just to test,
I wrote the following file:

library ieee;

use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use WORK.mylib1.all;



huge snip

Thanks

Morosh (gvnl@yahoo.fr)


Well "doh"! Orcad is a reasonably good analog schematic capture tool,
but it is not a front end to VHDL or Verilog; they have their own front
ends.
Actually, no. Orcad Express was a VHDL tool, that used Capture as its
front end, and not too bad a one at that. It was lost after the
purchase by Cadence.

Charlie
If you find it so fine for you. I had always accepted that VHDL was a move

to behavioral modeling (ignited by Conway-Meade) per the US military VHSIC
program; which was a move away transistor level modeling. Of course a good
generalized schematic capture tool might very well do the job. Don't get
me wrong, i liked Orcad back in the 1980's when i had a running version.
--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.
--Schiller