or gate simulation result

[TestUser13]

Hi,

Why q=z after end of simulation?

module test;
or u1 (a, b, q);

assign a = 1;
assign b = 1;
endmodule

 

[GaborSzakacs]

TestUser13 wrote:

Hi,

Why q=z after end of simulation?

module test;
or u1 (a, b, q);

assign a = 1;
assign b = 1;
endmodule

Unless you wrote your own "or" function, my guess
is that you have the ports in the wrong order.
Every gate I'm aware of has the output port first.
This is a classic example of the trouble you get
into when not using port names in the instantiation.
Unfortunately for built-in gate functions you don't
have that choice.

By the way, there's a good reason to put the output first
in the port list. There is always one gate output but
a variable number of gate inputs. Placing the output
at the end of the list would make it come at a different
port for each possible gate width.

You should write:

or u1 (q, a, b);

-- Gabor

 

[Cary R.]

On 2/6/2013 3:19 AM, TestUser13 wrote:

Hi,

Why q=z after end of simulation?

module test;
or u1 (a, b, q);

assign a = 1;
assign b = 1;
endmodule

Because the output of an or and all the other gates is the first
argument not the last. A buf and not gate can have multiple outputs, but
that is not very common.

Cary