optimizing my design

Hi,

I am targeting the design for XC2C512 coolrunner device. That's the
biggest device i could find. Are you aware of any larger CPLD device?
I have a dual-edge triggered clock i.e i have no other CPLD choice
other than the coolrunner series.

I find that i am falling short of a dozen macrocell counts. The
fitter report says it needs 524 macrocells and i have 512 macrocells
available to me :-(

I have tried to optimize the design to my best possible knowledge (and
my knowledge is not that profound).

Can anybody here advise me on how to squeeze the design a LITTLE BIT
more
to make it fit into the XC2C512 device?

Thanks.

 

[Dave Higton]

In message <1146402056.323900.256380@v46g2000cwv.googlegroups.com>
harikris@gmail.com wrote:

Hi,

I am targeting the design for XC2C512 coolrunner device. That's the
biggest device i could find. Are you aware of any larger CPLD device?
I have a dual-edge triggered clock i.e i have no other CPLD choice
other than the coolrunner series.

I find that i am falling short of a dozen macrocell counts. The
fitter report says it needs 524 macrocells and i have 512 macrocells
available to me :-(

I have tried to optimize the design to my best possible knowledge (and
my knowledge is not that profound).

Can anybody here advise me on how to squeeze the design a LITTLE BIT
more
to make it fit into the XC2C512 device?

Your question is too general. There is no way to answer it. Post
more details or ask more specific questions.

Dave

 

[john]

Hi,

Well most likely u have to change ur design. play with it as much as
possible like If you have state machines then try to reduce the state
machine size. try to decrease the input or output pins.

bye

 

[Thomas Stanka]

HI,

harikris@gmail.com schrieb:

I am targeting the design for XC2C512 coolrunner device. That's the
biggest device i could find. Are you aware of any larger CPLD device?
I have a dual-edge triggered clock i.e i have no other CPLD choice
other than the coolrunner series.

I read nothing in here, that prevents you from changing to larger
devices. So why not using a fpga?

I have tried to optimize the design to my best possible knowledge (and
my knowledge is not that profound).

Can anybody here advise me on how to squeeze the design a LITTLE BIT

If you have counters in your design you could inspect if you benefit
from changing the counter to:
- downto 0 instead of up to target value
- LFSR instead of sequential counter
- shiftregister instead of normal counter

Change from parallel operations to serial operations. Eg serial parity
takes one cylce per bit but needs only a FF plus a xor.

Inspect your target technology and try to find out which gates are free
(for your design) and change your design to use free resources even if
it need more resources than the standard sollution. Eg if you have free
registers use register doubling for signal buffering, if you lack
registers use inverter based signal buffering instead of register
doubling.

bye Thomas