optimization problem

[snehashis]

Dear Friends,
I am stuck with a problem.I want to design a fast multiplier(8bit x
8bit).I designed a wallace tree multiplier(fully combinational) with
adders as logarithmic and have taken into consideration some other area
optimization techniques.Yet my module shows both area and maxm
combinational block delay constraint almost 1.5 times the default one.
input [7:0]a,b;
output [15:0]c;
assign c=a*b;

Can anybody plz tell me what is the reason behind this problem?I am using
xilinx environment.
snehashis

 

[Karl Monell]

Did you select the correct speed grade for your Xilinx device?
Do you know that there is a lot of information (application notes etc)
available at Xilinx web-site about how to design multipliers for
most Xilinx families?
Do you use xilinx XST or another synthesis tool?
Regards,
Karl.

snehashis wrote:

Dear Friends,
I am stuck with a problem.I want to design a fast multiplier(8bit x
8bit).I designed a wallace tree multiplier(fully combinational) with
adders as logarithmic and have taken into consideration some other area
optimization techniques.Yet my module shows both area and maxm
combinational block delay constraint almost 1.5 times the default one.
input [7:0]a,b;
output [15:0]c;
assign c=a*b;

Can anybody plz tell me what is the reason behind this problem?I am using
xilinx environment.
snehashis

 

I designed a wallace tree multiplier(fully combinational) with
adders as logarithmic and have taken into consideration some other
area
optimization techniques.Yet my module shows both area and maxm
combinational block delay constraint almost 1.5 times the default
one.

Can anybody plz tell me what is the reason behind this problem?I am
using
xilinx environment.

Perhaps the default 8x8 multiplier for that environment is almost 1.5x
better than yours.

 

[snehashis]

I am using xilinx xst.And could you plz elaborate on the correct spped
grade problem?I am a not familiar with the speed grade..
thanks,
snehashis

 

[snehashis]

Is it possible to know the architecture of the in-built modules in xilinx
xst or at least get some idea on that?
snehashis

 

[Karl Monell]

Let us assume that you are using a Xilinx XC4VLX25-10FF668C.
The speed grade is the "-10" part of the article number.
For this particular part there is three speed grade: -10, -11 & -12.
If the comparison data for the multiplier is valid for the fastest speed
and you are running your synthesis tool with the slowest speed grade
selected, then it is likely that you get a 50 % timing difference.
Regards,
Karl.

snehashis wrote:

I am using xilinx xst.And could you plz elaborate on the correct spped
grade problem?I am a not familiar with the speed grade..
thanks,
snehashis

 

[Karl Monell]

A good place to start is Xilinx's Libraries Guide:
http://toolbox.xilinx.com/docsan/data/alliance/lib/lib.htm
Regards,
Karl.

snehashis wrote:

Is it possible to know the architecture of the in-built modules in xilinx
xst or at least get some idea on that?
snehashis