Opinions on High Speed Design Book ?

[Dave Garnett]

Any opinions out there on 'Handbook of Digital Techniques for High Speed
Design' by Tom Granberg (Prentice Hall, ISBN 013142291X ) ?

--
Life is tough - sometimes you get nougat.




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[PeteS]

I can't say I have seen that one, but I have used 'High-Speed Digital
Design: A Handbook of Black Magic', by Howard Johnson (he also runs a
company, http://www.sigcon.com).

I used this as a reference for those times my memory failed me when I
was designing multiple high speed systems on one board (speeds from
100MHz to 2.5GHz on copper) and I found it wonderful.

What would matter, of course, is what you are looking for out of the
book. Is there some particular project you have in mind, or just
looking generally?

Cheers

PeteS

 

[Dave Garnett]

"PeteS" <ps@fleetwoodmobile.com> wrote in message
news:1110990685.475784.179410@z14g2000cwz.googlegroups.com...

I can't say I have seen that one, but I have used 'High-Speed Digital
Design: A Handbook of Black Magic', by Howard Johnson (he also runs a
company, http://www.sigcon.com).

I used this as a reference for those times my memory failed me when I
was designing multiple high speed systems on one board (speeds from
100MHz to 2.5GHz on copper) and I found it wonderful.

What would matter, of course, is what you are looking for out of the
book. Is there some particular project you have in mind, or just
looking generally?

Cheers

PeteS

Yes, I have Johnson's book, and indeed it is useful - but I have come across
situations which it does not really answer.

Simple example - FPGAs require lots of decoupling caps. For my prototype
boards I put the caps on the underside of the board and everything works.
However, this costs more in production, so the pressure is to move
everything to one side. Peering at other boards I see that it is quite
common to end up with a ring of bypass caps around the fpga - but space is
tight there and such a placement will inevitably increase trace lengths. I
guess that one answer is to have more (perhaps partial) power planes, but
that increases the board cost ! Right now I do not have a good metric for
deciding which route to go - perhaps I have to build a board that doesn't
quite work to learn what the limits are !

In the end, if a book provides one simple idea or fact that removes a
respin, it has paid for itself many times over.

Oh, and they want the board to go twice as fast ...

regards,
Dave




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[John Woodgate]

I read in sci.electronics.design that Dave Garnett <dave.garnett@metapur
ple.co.uk> wrote (in <423863c5$1_3@127.0.0.1&gt about 'Opinions on High
Speed Design Book ?', on Wed, 16 Mar 2005:

Right now I do not have a
good metric for deciding which route to go - perhaps I have to build a
board that doesn't quite work to learn what the limits are !

The problem with trying less than 'perfect' bypassing is that your trial
board may work but you have no way of determining how near the bone it
is. I'd go for your best solution, and justify it on the grounds that
you don't want to find another solution is 'not quite good enough' when
you are in production. Especially if the manufacturer 'improves' the
device you are trying to tame.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

 

[John Larkin]

On Wed, 16 Mar 2005 16:59:18 -0000, "Dave Garnett"
<dave.garnett@metapurple.co.uk> wrote:

Yes, I have Johnson's book, and indeed it is useful - but I have come across
situations which it does not really answer.

And there are places where it's irrelevant, or flat wrong.

Simple example - FPGAs require lots of decoupling caps. For my prototype
boards I put the caps on the underside of the board and everything works.
However, this costs more in production, so the pressure is to move
everything to one side. Peering at other boards I see that it is quite
common to end up with a ring of bypass caps around the fpga - but space is
tight there and such a placement will inevitably increase trace lengths. I
guess that one answer is to have more (perhaps partial) power planes, but
that increases the board cost ! Right now I do not have a good metric for
deciding which route to go -

I generally use 4 caps per supply, topside, maybe 0.2 inches away from
the edges of the chip, with an internal plane or hefty poured island
per supply voltage. Near the corners of the chip is good to minimize
interfering with topside trace routing, but exact location doesn't
really matter.

perhaps I have to build a board that doesn't
quite work to learn what the limits are !

On a multilayer board with proper power pours, that's actually hard to
do. Just keep the power:ground dielectrics thin.

John

 

[Terry Given]

John Larkin wrote:

On Wed, 16 Mar 2005 16:59:18 -0000, "Dave Garnett"
dave.garnett@metapurple.co.uk> wrote:


Yes, I have Johnson's book, and indeed it is useful - but I have come across
situations which it does not really answer.


And there are places where it's irrelevant, or flat wrong.

Please Elucidate....

Simple example - FPGAs require lots of decoupling caps. For my prototype
boards I put the caps on the underside of the board and everything works.
However, this costs more in production, so the pressure is to move
everything to one side. Peering at other boards I see that it is quite
common to end up with a ring of bypass caps around the fpga - but space is
tight there and such a placement will inevitably increase trace lengths. I
guess that one answer is to have more (perhaps partial) power planes, but
that increases the board cost ! Right now I do not have a good metric for
deciding which route to go -


I generally use 4 caps per supply, topside, maybe 0.2 inches away from
the edges of the chip, with an internal plane or hefty poured island
per supply voltage. Near the corners of the chip is good to minimize
interfering with topside trace routing, but exact location doesn't
really matter.


perhaps I have to build a board that doesn't
quite work to learn what the limits are !


On a multilayer board with proper power pours, that's actually hard to
do. Just keep the power:ground dielectrics thin.

John

Cheers
Terry

 

[John Larkin]

On Thu, 17 Mar 2005 10:55:55 +1300, Terry Given <my_name@ieee.org>
wrote:

John Larkin wrote:
On Wed, 16 Mar 2005 16:59:18 -0000, "Dave Garnett"
dave.garnett@metapurple.co.uk> wrote:


Yes, I have Johnson's book, and indeed it is useful - but I have come across
situations which it does not really answer.


And there are places where it's irrelevant, or flat wrong.


Please Elucidate....

Too many to list them all. But..

eq 7.6 "within an order of magnitude". How useful is that? How pompous
is that?

p 261, "An interesting consequence..." is silly, double so when
qualified by the next sentence.

Same page, "At the point..." gets back to the incredible illusions
lots of people have about return currents.


p 265, power rule 2 is strange.

279, "Combining TTL..." is contentless. Big DUH. Lots of his writing
is annoying like this. Same page, bullet "To reduce noise leakage" is
nonsense. What is "noise leakage" anyhow?

312, sec 9.5, is absurd. Return current fetishes again.

316, in the box: "Always fails". Gimme a break.

12.12.1 Claims 20,000 * 8KHz = 154.4 MHz.



Well, you get the idea. The book is a mixture of good stuff and
nonsense. If you know enough to tell which is which, you don't need
the book!


John

 

[Terry Given]

John Larkin wrote:

On Thu, 17 Mar 2005 10:55:55 +1300, Terry Given <my_name@ieee.org
wrote:


John Larkin wrote:

On Wed, 16 Mar 2005 16:59:18 -0000, "Dave Garnett"
dave.garnett@metapurple.co.uk> wrote:



Yes, I have Johnson's book, and indeed it is useful - but I have come across
situations which it does not really answer.


And there are places where it's irrelevant, or flat wrong.


Please Elucidate....





Too many to list them all. But..

eq 7.6 "within an order of magnitude". How useful is that? How pompous
is that?

not very

p 261, "An interesting consequence..." is silly, double so when
qualified by the next sentence.

LMAO! It says, btw "An interesting consequence of this connection is
that an inner-layer trace radiates no more or less than an outer layer
trace. THIS IS PARTICULARLY TRUE FOR TRACES NEAR THE EDGE OF THE BOARD"

Same page, "At the point..." gets back to the incredible illusions
lots of people have about return currents.

fair call.

p 265, power rule 2 is strange.

and one I violate all the time. Mostly because ground is the reference,
and as long as I have enough noise margin I dont care a fig how wobbly
Vcc gets.

279, "Combining TTL..." is contentless. Big DUH. Lots of his writing
is annoying like this. Same page, bullet "To reduce noise leakage" is
nonsense. What is "noise leakage" anyhow?

not just contentless, but meaningless too. Why stop there: "combining 2
or more gates in one system without considering the system design
consequences is not a good idea"

Hey, lets abridge it:
"Not considering the system design consequences is not a good idea"

aka

"some semblence of understanding is required"

312, sec 9.5, is absurd. Return current fetishes again.

here I dont quite get your complaint. its all about considering (and
minimising) the total inductance of the physical loop around which
current flows.

But fig 9.11 WILL function properly at high speeds - it will ring like a
SOB, which is the proper function of such a physical construction.

316, in the box: "Always fails". Gimme a break.

So all we need to do is cover it with a thin layer of pvc, to avoid
"exposure" eh? especially those nano-inch exposed wires

12.12.1 Claims 20,000 * 8KHz = 154.4 MHz.

Perhaps he was using Roberts special abacus, and mis-counted the number
of beads.

Well, you get the idea. The book is a mixture of good stuff and
nonsense. If you know enough to tell which is which, you don't need
the book!


John

I would argue that:

1) its a damn good start

2) if you read and understand it, it can function as its own bullshit
detector.

3) compared to, say, Tsaliovich's book on cable shielding, its a joy to read

4) compared to, say, anything ever published by TAB books (or "authored"
by Irving Gottlieb or Randy Sloane), it contains useful information with
enough formulae and references to point you in the right direction


How about p.376 "every clock oscillator contains a very fine
high-frequency amplifier"

what, extremely thin? Shitty clock bricks, by definition, have shitty hf
amplifiers....

Cheers
Terry