Y
Yottameter
Guest
I'm currently using parameters to open up a file:
$readmemb({ROOT_DIR, LOCAL_DIR, TEST,TEST_SUFFIX}, mem);
If I change TEST to a register declaration:
reg [40*8:0] TEST;//
How can I remove the whitespace at the beginning of the register, so the
concatenation above works? The concatenation results in a lot of
undefined values at the beginning of TEST, ie 40-(length(TEST)). I'm
really trying to 'resize' the register, so I think my question is
impossible to answer.
Seems like I'm missing a concat for strings in verilog.
The reason I'd like to do this is that I'd like to pass in ROOT_DIR,
LOCAL_DIR, TEST and TEST_SUFFIX as command line options using
$value$plusargs as opposed to using parameter modifiers on the command line.
Thanks.
$readmemb({ROOT_DIR, LOCAL_DIR, TEST,TEST_SUFFIX}, mem);
If I change TEST to a register declaration:
reg [40*8:0] TEST;//
How can I remove the whitespace at the beginning of the register, so the
concatenation above works? The concatenation results in a lot of
undefined values at the beginning of TEST, ie 40-(length(TEST)). I'm
really trying to 'resize' the register, so I think my question is
impossible to answer.
Seems like I'm missing a concat for strings in verilog.
The reason I'd like to do this is that I'd like to pass in ROOT_DIR,
LOCAL_DIR, TEST and TEST_SUFFIX as command line options using
$value$plusargs as opposed to using parameter modifiers on the command line.
Thanks.