Open Verification Libiary Free Download

[Davy]

Hi all,

I am a Verilog user and I want to find some tools do assertion(like C's
assert()).

I found Open Verification Libiary(OVL) has been updated. And it is free
for download( http://www.accellera.org/activities/ovl/ ).

I hope to use it in the near future.

Anyone has used it yet? Please give some comment. Thanks!

Best regards,
Davy

 

[Uncle Noah]

not used it but does anybody know if it is going to be ported to VHDL
too? (like the old OVLs)

Regards
Nikolaos Kavvadias

 

[anupam]

hi,
Ya, i have used the OVLs for one of my projects
Its good for verification if you have ample time ...
You need to write all the possible assertions for a block and yet at
later some point you will notice that there are some more to be written
.......
Try system Verilog assertions ,they are smart but a bit difficult to
learn....

regards,
Anupam Jain

 

[anupam]

Theres one library in VHDL too like in verilog ....


regards,
Anupam Jain