open sparc t1

[johnhull2008]

Question about the following code:

http://www.opensparc.net/pubs/t1/html/sctag_mbctl.v.html#adder_1b
http://www.opensparc.net/pubs/t1/html/sctag_mbctl.v.html#adder_4b

Is there a reason why the adders had to be coded this way?
I have some experience doing ASIC design for a consumer electronics
company in the past and never had to write a bit-level behavior to
just do addition.
Is this a normal thing to do or is it just for SUN?
My guess is that they do not use commercial synthesis tools for
microprocessors, and that is why they are coding at such a low level,
but I am not sure.

 

[Muzaffer Kal]

On Fri, 11 Jul 2008 22:48:07 -0700 (PDT), johnhull2008
<johnhull2008@gmail.com> wrote:

Question about the following code:

http://www.opensparc.net/pubs/t1/html/sctag_mbctl.v.html#adder_1b
http://www.opensparc.net/pubs/t1/html/sctag_mbctl.v.html#adder_4b

Is there a reason why the adders had to be coded this way?
I have some experience doing ASIC design for a consumer electronics
company in the past and never had to write a bit-level behavior to
just do addition.
Is this a normal thing to do or is it just for SUN?
My guess is that they do not use commercial synthesis tools for
microprocessors, and that is why they are coding at such a low level,
but I am not sure.

It's very likely that in the early days all of these cells were
designed in schematic and the layout was custom because synthesis
tools were lacking and when that was no longer feasible/needed, they
just generated netlists from the schematics and started using
synthesis.
Actually if you look at the tools needed for Chip Design and
verification, Synopsys Design compiler is one of them. It's very
likely that today most of any process is designing (having designed?)
is being implemented with a synthesis tool. Probably only (portions
of) the data-path is being done custom anymore.
The nice thing about synthesis is that depending on your speed
requirements a regular adder can be implemented with a ripple-carry
too instead of being hard-wired to a carry look ahead adder always.
For an FPGA a carry lookahead adder may not even be the fastest as it
has to be implemented in the fabric but there are hard-wired fast
carry chains which give you faster ones.