Open Source Projects

[Arpan]

Hi All,
I am looking for interesting open source projects in verilog/vhdl/
systemverilog design where there is a scope to contribute. Maybe
providing some verification related code development (SV assertions
for e.g.) on top of existing RTL, providing for simulation/synthesis/
timing script development etc. I know opencores is a good place to
start looking into, but it's still a reasonably big search space and
any specific pointers (both within opencores and otherwise) would
help. As a matter of fact, if anyone has other ideas/links etc by
which someone could contribute to the open source h/w design please
let us all know.

Looking forward to hearing suggestions from everyone.

Thanks and Regards

 

[Jeremy Bennett]

On Fri, 31 Jul 2009 22:41:32 -0700, Arpan wrote:

I am looking for interesting open source projects in verilog/vhdl/
systemverilog design where there is a scope to contribute. Maybe
providing some verification related code development (SV assertions for
e.g.) on top of existing RTL, providing for simulation/synthesis/ timing
script development etc. I know opencores is a good place to start
looking into, but it's still a reasonably big search space and any
specific pointers (both within opencores and otherwise) would help. As a
matter of fact, if anyone has other ideas/links etc by which someone
could contribute to the open source h/w design please let us all know.

Hi Arpan,

You should try asking the same question on the OpenCores forums as well.
Their flagship project is the OpenRISC 1200, which could certainly
benefit from extension of its verification framework. There are loads of
smaller projects, which are always looking for help.

You could also look at the Open Hardware Repository (www.ohwr.org), which
is run from CERN. Rather a narrower focus on the sort of hardware that is
useful in particle accelerators!

HTH,


Jeremy