Open/Free HLS weapon of choice ?

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Leonardo Capossio

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Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.
 
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera)..

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.
Click to expand...

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.
While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).

Yaman
 
El martes, 9 de junio de 2015, 12:11:54 (UTC-3), Yaman Umuroglu escribió:
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.
While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).

Yaman
Click to expand...

Yes, I have already looked at Chisel, and I do agree with you. It seems to have good performance, but it still is very RTL-like, and is not as capable (or supported) as VHDL or Verilog at RTL-level (for example having specific architecture instances like RAMs, ROMs or even more important I/O primitives is difficult). It just seems like the effort to learn this language compared to the abstraction/easiness at algorithm level is not very high.

LegUp on the other hand, would provide more abstraction, but it has sub-par results (according to the paper I posted it beats the software implementation in performance in most cases, but is always bested by far by other languages).
 
El martes, 9 de junio de 2015, 13:39:23 (UTC-3), Christopher Felton escribió:
On 6/9/2015 10:11 AM, Yaman Umuroglu wrote:
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.

I don't think RTL is the correct term here but the point
is you feel it requires a lower-lower level abstraction
than you would like. Chisel is a bread of the functional
language based HDLs. You start with a basic building block
(function, or register in HDL) and scale-up quickly - at
least that is the idea (?).

While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).

I will never understand how any C based language will be
considered HLS! Saw a funny tweet the other day:

Computer Science: "In low-level languages like C"
Computer Engineering: "In high-level languages like C"

Regards,
Chris
Click to expand...

Well, the wikipedia page defines it so (http://en.wikipedia.org/wiki/High-level_synthesis), not saying this is the ultimate authority in the matter, but you at least have to counter this assertion with something better than a tweet.

I guess C is low-level in computer science because you can actually trace most of the code one-to-one or one-to-many from C to assembler. In hardware description this is far more difficult to do, some statements are not literally translated into HDL code, but rather interpreted, and many assumptions are made. They are different fields. Keep in mind C will not be the highest HDL language ever, but the first of them (or one of the first).
 
El martes, 9 de junio de 2015, 15:08:40 (UTC-3), Christopher Felton escribió:
On 6/9/2015 12:14 PM, Leonardo Capossio wrote:
El martes, 9 de junio de 2015, 13:39:23 (UTC-3), Christopher Felton escribió:
On 6/9/2015 10:11 AM, Yaman Umuroglu wrote:
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.

I don't think RTL is the correct term here but the point
is you feel it requires a lower-lower level abstraction
than you would like. Chisel is a bread of the functional
language based HDLs. You start with a basic building block
(function, or register in HDL) and scale-up quickly - at
least that is the idea (?).

While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg..utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).

I will never understand how any C based language will be
considered HLS! Saw a funny tweet the other day:

Computer Science: "In low-level languages like C"
Computer Engineering: "In high-level languages like C"

Regards,
Chris

Well, the wikipedia page defines it so (http://en.wikipedia.org/wiki/High-level_synthesis), not saying this is the ultimate authority in the matter, but you at least have to counter this assertion with something better than a tweet.

Why? I wasn't trying to correct anything just stating
how I am dumbfounded at the term! Do you disagree with
low-high statement? I think it is rather fitting :)

If this is the unfortunate state of terminology, what do
we call synthesis of non C languages? Ultra-high,
up-in-smoke, etc. etc.

I think this is a better description: "algorithm to gates"
http://mesl.ucsd.edu/gupta/pubs/HLSRetrospective08Rev3.pdf
(there is a book with a similar title)

The HLS term should be language agnostic, it is silly to
tie it to C based languages!
Click to expand...

The tweet is true and points at a funny fact. But that doesn't mean that C is not a high level language when talking about synthesis.

The HLS term IS agnostic, the wikipedia article is only focusing about C which is also rather biased (but probably because it is a well known language, and at the time of creation C was considered high level), but mentions: "High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis...". It even includes your "algorithmic" preference for the term as "algorithmic synthesis".

I guess C is low-level in computer science because you can actually trace most of the code one-to-one or one-to-many from C to assembler. In hardware description this is far more difficult to do, some statements are not literally translated into HDL code, but rather interpreted, and many assumptions are made. They are different fields. Keep in mind C will not be the highest HDL language ever, but the first of them (or one of the first).


Probably because the name was coined in the early 90s
(or earlier). In my opinion C synthesis is pointless.

I think these guys kinda got it right (but they based
their language on C constructs also - confusing):
https://blog.synflow.com/numbers-dont-lie-there-is-virtually-no-interest-in-high-level-synthesis/

Regards,
Chris
Click to expand...

The fact that there are less google searches is a fact that can't be ignored, but it does not mean it is the end. Someone will get it right eventually, and the thing will become very popular, probably at the same time that FPGAs become very popular (mainstream I mean, like arduino with microcontrollers). If a certain person (or company) is going to make a genius invention (or lead it) in the next two years, then he is thinking about this invention starting from now, or even before (and he is certainly at that point very familiar with the problem that he will be tackling). I cannot point any source, but I think it makes at least more than 50% of the cases (the rest just happened to stumble into greatness by chance).
 
El martes, 9 de junio de 2015, 17:00:23 (UTC-3), Leonardo Capossio escribió:
El martes, 9 de junio de 2015, 15:08:40 (UTC-3), Christopher Felton escribió:
On 6/9/2015 12:14 PM, Leonardo Capossio wrote:
El martes, 9 de junio de 2015, 13:39:23 (UTC-3), Christopher Felton escribió:
On 6/9/2015 10:11 AM, Yaman Umuroglu wrote:
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.

I don't think RTL is the correct term here but the point
is you feel it requires a lower-lower level abstraction
than you would like. Chisel is a bread of the functional
language based HDLs. You start with a basic building block
(function, or register in HDL) and scale-up quickly - at
least that is the idea (?).

While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).

I will never understand how any C based language will be
considered HLS! Saw a funny tweet the other day:

Computer Science: "In low-level languages like C"
Computer Engineering: "In high-level languages like C"

Regards,
Chris

Well, the wikipedia page defines it so (http://en.wikipedia.org/wiki/High-level_synthesis), not saying this is the ultimate authority in the matter, but you at least have to counter this assertion with something better than a tweet.

Why? I wasn't trying to correct anything just stating
how I am dumbfounded at the term! Do you disagree with
low-high statement? I think it is rather fitting :)

If this is the unfortunate state of terminology, what do
we call synthesis of non C languages? Ultra-high,
up-in-smoke, etc. etc.

I think this is a better description: "algorithm to gates"
http://mesl.ucsd.edu/gupta/pubs/HLSRetrospective08Rev3.pdf
(there is a book with a similar title)

The HLS term should be language agnostic, it is silly to
tie it to C based languages!


The tweet is true and points at a funny fact. But that doesn't mean that C is not a high level language when talking about synthesis.

The HLS term IS agnostic, the wikipedia article is only focusing about C which is also rather biased (but probably because it is a well known language, and at the time of creation C was considered high level), but mentions: "High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis...". It even includes your "algorithmic" preference for the term as "algorithmic synthesis".


I guess C is low-level in computer science because you can actually trace most of the code one-to-one or one-to-many from C to assembler. In hardware description this is far more difficult to do, some statements are not literally translated into HDL code, but rather interpreted, and many assumptions are made. They are different fields. Keep in mind C will not be the highest HDL language ever, but the first of them (or one of the first).


Probably because the name was coined in the early 90s
(or earlier). In my opinion C synthesis is pointless.

I think these guys kinda got it right (but they based
their language on C constructs also - confusing):
https://blog.synflow.com/numbers-dont-lie-there-is-virtually-no-interest-in-high-level-synthesis/

Regards,
Chris


The fact that there are less google searches is a fact that can't be ignored, but it does not mean it is the end. Someone will get it right eventually, and the thing will become very popular, probably at the same time that FPGAs become very popular (mainstream I mean, like arduino with microcontrollers). If a certain person (or company) is going to make a genius invention (or lead it) in the next two years, then he is thinking about this invention starting from now, or even before (and he is certainly at that point very familiar with the problem that he will be tackling). I cannot point any source, but I think it makes at least more than 50% of the cases (the rest just happened to stumble into greatness by chance).
Click to expand...

For the record the interest in high-level synthesis is slowly decreasing but saw an increase starting from 2012. But MORE interesting is the fact that FPGA alone as a search term is decreasing since 2004, and I don't think FPGA are going obsolete any time soon. Turns out that this "EDA" developer article was really biased (https://www.google.com/trends/explore#q=fpga&cmpt=q&tz=). It is clear that HLS is not a mainstream search term, but it is not over (and by HLS, I am talking about any language that infers VHDL/Verilog or gate-level-description)
 
On 6/9/2015 10:11 AM, Yaman Umuroglu wrote:
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.
Click to expand...

I don't think RTL is the correct term here but the point
is you feel it requires a lower-lower level abstraction
than you would like. Chisel is a bread of the functional
language based HDLs. You start with a basic building block
(function, or register in HDL) and scale-up quickly - at
least that is the idea (?).

> While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).

I will never understand how any C based language will be
considered HLS! Saw a funny tweet the other day:

Computer Science: "In low-level languages like C"
Computer Engineering: "In high-level languages like C"

Regards,
Chris
 
On 6/9/2015 12:14 PM, Leonardo Capossio wrote:
El martes, 9 de junio de 2015, 13:39:23 (UTC-3), Christopher Felton escribió:
On 6/9/2015 10:11 AM, Yaman Umuroglu wrote:
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.

I don't think RTL is the correct term here but the point
is you feel it requires a lower-lower level abstraction
than you would like. Chisel is a bread of the functional
language based HDLs. You start with a basic building block
(function, or register in HDL) and scale-up quickly - at
least that is the idea (?).

While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost).

I will never understand how any C based language will be
considered HLS! Saw a funny tweet the other day:

Computer Science: "In low-level languages like C"
Computer Engineering: "In high-level languages like C"

Regards,
Chris

Well, the wikipedia page defines it so (http://en.wikipedia.org/wiki/High-level_synthesis), not saying this is the ultimate authority in the matter, but you at least have to counter this assertion with something better than a tweet.
Click to expand...

Why? I wasn't trying to correct anything just stating
how I am dumbfounded at the term! Do you disagree with
low-high statement? I think it is rather fitting :)

If this is the unfortunate state of terminology, what do
we call synthesis of non C languages? Ultra-high,
up-in-smoke, etc. etc.

I think this is a better description: "algorithm to gates"
http://mesl.ucsd.edu/gupta/pubs/HLSRetrospective08Rev3.pdf
(there is a book with a similar title)

The HLS term should be language agnostic, it is silly to
tie it to C based languages!

I guess C is low-level in computer science because you can actually trace most of the code one-to-one or one-to-many from C to assembler. In hardware description this is far more difficult to do, some statements are not literally translated into HDL code, but rather interpreted, and many assumptions are made. They are different fields. Keep in mind C will not be the highest HDL language ever, but the first of them (or one of the first).
Click to expand...

Probably because the name was coined in the early 90s
(or earlier). In my opinion C synthesis is pointless.

I think these guys kinda got it right (but they based
their language on C constructs also - confusing):
https://blog.synflow.com/numbers-dont-lie-there-is-virtually-no-interest-in-high-level-synthesis/

Regards,
Chris
 
On Tuesday, June 9, 2015 at 10:31:03 PM UTC+2, Leonardo Capossio wrote:
El martes, 9 de junio de 2015, 17:00:23 (UTC-3), Leonardo Capossio escribió:
El martes, 9 de junio de 2015, 15:08:40 (UTC-3), Christopher Felton escribió:
On 6/9/2015 12:14 PM, Leonardo Capossio wrote:
El martes, 9 de junio de 2015, 13:39:23 (UTC-3), Christopher Felton escribió:
On 6/9/2015 10:11 AM, Yaman Umuroglu wrote:
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
Hello all, I would like to know which open or free HLS (High Level Synthesis) tools are gaining widespread use, or are more likely to survive, because at the time there seems to be too many, and the advantages of each of them are not quite clear. The HLS we are talking about should generate synthesizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head with only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far by either directly using the generated Verilog, or wrapping it as IP cores for importing into Vivado. However, I wouldn't really call it "HLS" -- while it gives higher productivity compared to Verilog or VHDL, Chisel code is still very close to RTL and requires RTL-like thinking.

I don't think RTL is the correct term here but the point
is you feel it requires a lower-lower level abstraction
than you would like. Chisel is a bread of the functional
language based HDLs. You start with a basic building block
(function, or register in HDL) and scale-up quickly - at
least that is the idea (?).

While I've only looked at it briefly myself, LegUp seems to be a worthy open/free HLS alternative that is actively maintained (http://legup.eecg.utoronto.ca/). I don't think they support Xilinx for the time being, but the abstractions made by the framework should make it straightforward to port to Xilinx FPGAs (i.e defining the primitives and their relative cost)..

I will never understand how any C based language will be
considered HLS! Saw a funny tweet the other day:

Computer Science: "In low-level languages like C"
Computer Engineering: "In high-level languages like C"

Regards,
Chris

Well, the wikipedia page defines it so (http://en.wikipedia.org/wiki/High-level_synthesis), not saying this is the ultimate authority in the matter, but you at least have to counter this assertion with something better than a tweet.

Why? I wasn't trying to correct anything just stating
how I am dumbfounded at the term! Do you disagree with
low-high statement? I think it is rather fitting :)

If this is the unfortunate state of terminology, what do
we call synthesis of non C languages? Ultra-high,
up-in-smoke, etc. etc.

I think this is a better description: "algorithm to gates"
http://mesl.ucsd.edu/gupta/pubs/HLSRetrospective08Rev3.pdf
(there is a book with a similar title)

The HLS term should be language agnostic, it is silly to
tie it to C based languages!


The tweet is true and points at a funny fact. But that doesn't mean that C is not a high level language when talking about synthesis.

The HLS term IS agnostic, the wikipedia article is only focusing about C which is also rather biased (but probably because it is a well known language, and at the time of creation C was considered high level), but mentions: "High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis...". It even includes your "algorithmic" preference for the term as "algorithmic synthesis".


I guess C is low-level in computer science because you can actually trace most of the code one-to-one or one-to-many from C to assembler. In hardware description this is far more difficult to do, some statements are not literally translated into HDL code, but rather interpreted, and many assumptions are made. They are different fields. Keep in mind C will not be the highest HDL language ever, but the first of them (or one of the first).


Probably because the name was coined in the early 90s
(or earlier). In my opinion C synthesis is pointless.

I think these guys kinda got it right (but they based
their language on C constructs also - confusing):
https://blog.synflow.com/numbers-dont-lie-there-is-virtually-no-interest-in-high-level-synthesis/

Regards,
Chris


The fact that there are less google searches is a fact that can't be ignored, but it does not mean it is the end. Someone will get it right eventually, and the thing will become very popular, probably at the same time that FPGAs become very popular (mainstream I mean, like arduino with microcontrollers). If a certain person (or company) is going to make a genius invention (or lead it) in the next two years, then he is thinking about this invention starting from now, or even before (and he is certainly at that point very familiar with the problem that he will be tackling). I cannot point any source, but I think it makes at least more than 50% of the cases (the rest just happened to stumble into greatness by chance).

For the record the interest in high-level synthesis is slowly decreasing but saw an increase starting from 2012. But MORE interesting is the fact that FPGA alone as a search term is decreasing since 2004, and I don't think FPGA are going obsolete any time soon. Turns out that this "EDA" developer article was really biased (https://www.google.com/trends/explore#q=fpga&cmpt=q&tz=). It is clear that HLS is not a mainstream search term, but it is not over (and by HLS, I am talking about any language that infers VHDL/Verilog or gate-level-description)
Click to expand...

I think the tweet mentioned summarizes this discussion pretty well; there is no rigid definition of the "high-level" in high-level synthesis :).
For me it's not very high level as long as it is converting between equivalent abstractions (e.g. Chisel internally creates a directed acyclic graph of registers, muxes and operators directly from the description, which can be viewed as RTL).

Regardless, be it C-to-gates (Vivado HLS/SDSoC) or OpenCL for FPGAs, it seems to me that the trend is picking up for "FPGAs for software programmers" (see also http://arxiv.org/abs/1408.4423). Probably with good reason seeing how several major players seem to be interested in making FPGAs "the next big thing in acceleration" -- Intel acquiring Altera and rumors of Xeons with integrated FPGAs, IBM OpenPOWER systems with FPGA accelerators over CAPI, Micron acquiring high-performance FPGA card makers Convey and Pico Computing, and so on. As long as the ecosystem thrives and the tools improve, I'm happy :)

Yaman
 
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