Open Collector Circuit - How to Simulate?

D

Drew

Guest
Hi all,

I need Open Collector Active-Low analog circuit's logical
representation. I am having pretty hard time putting it togather. I
used bidirectional tristated bus, but it doesnt solve my problem.
There are some contentions as I have to read what I write to the Bidir
Pin (always) and at some point the Bidir Pin works as an output too.

Please help,
Drew
 
On 20 Jul 2004 09:13:40 -0700, dhruvish@gmail.com (Drew) wrote:

Hi all,

I need Open Collector Active-Low analog circuit's logical
representation. I am having pretty hard time putting it togather. I
used bidirectional tristated bus, but it doesnt solve my problem.
There are some contentions as I have to read what I write to the Bidir
Pin (always) and at some point the Bidir Pin works as an output too.
Actually it should. An open collector (which would be for almost all
fpgas) configuration can be modeled with a tri-state output which can
be driven low or tri-stated, not driven-high. You should be able to
use a regular tri-state bi-directional io to do what you need.

Try this:

module od_io(pad, in, oeb);
inout pad;
output in;
input oeb;

wire pad = oeb ? 1'bz : 1'b0;
wire in = pad;

endmodule

this should map to a bi-dir io or you can instantiate one from your
device's library.
 
Drew wrote:
Hi all,

I need Open Collector Active-Low analog circuit's logical
representation. I am having pretty hard time putting it togather. I
used bidirectional tristated bus, but it doesnt solve my problem.
There are some contentions as I have to read what I write to the Bidir
Pin (always) and at some point the Bidir Pin works as an output too.
You didn't say what you are modeling in. Assuming you are using VHDL or
Verilog, a tri-state bus is modeled using STD_LOGIC. A tri-state open
collector driver will drive either a '0' or an 'X'. Any of these
drivers can overdrive the 'X' of another when they drive a '0' which is
a "strong" drive. If you want to model a pullup resistor, drive the net
with a constant 'H' from another source. This is a "weak" high and will
overdrive the 'X', but be overdriven by the '0'. In most logic
functions, the 'H' will be treated the same as a '1'. Or you may have
to convert to '0', '1' before using this bus as an input.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
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