R
ram
Guest
Hi Group,
I am designing a simple core to add to the opb bus using opb_ssp0
package.
The core has 2 register, and I am tryin to write a value and read from
them.
But when I do that its giving me an output thats wierd, whenever I
write a even number to the register I read back an odd number ( one
greater then the even number )but for odd numbers its ok.
have a look at the following code example and the results.
/* write to register */
XIut32( (XIo_Address)(XPAR_MY_COUNTER_BASEADDR + REG_A_OFFSET) ,
0x32 )
/*Read from register */
reg_a = XIo_In32( (XIo_Address)XPAR_MY_COUNTER_BASEADDR + REG_A_OFFSET
);
/* Display result */
XUartLite_SendByte( XPAR_RS232_BASEADDR, reg_a );
In the above example the result is 0x33.
Does anybody have the same problem ,i will appreciate if somebody
could help me to point out the mistake i am doing.
Thanx for your time and support
Ram
I am designing a simple core to add to the opb bus using opb_ssp0
package.
The core has 2 register, and I am tryin to write a value and read from
them.
But when I do that its giving me an output thats wierd, whenever I
write a even number to the register I read back an odd number ( one
greater then the even number )but for odd numbers its ok.
have a look at the following code example and the results.
/* write to register */
XIut32( (XIo_Address)(XPAR_MY_COUNTER_BASEADDR + REG_A_OFFSET) ,
0x32 )
/*Read from register */
reg_a = XIo_In32( (XIo_Address)XPAR_MY_COUNTER_BASEADDR + REG_A_OFFSET
);
/* Display result */
XUartLite_SendByte( XPAR_RS232_BASEADDR, reg_a );
In the above example the result is 0x33.
Does anybody have the same problem ,i will appreciate if somebody
could help me to point out the mistake i am doing.
Thanx for your time and support
Ram