OPAMP simulation and PROTEL

  • Thread starter Edgar Y. Lobachevskiy
  • Start date
E

Edgar Y. Lobachevskiy

Guest
Hi all:

I am running a simulation on basic integrator using PROTEL. when I
have a bleeding resistor and capacitor in parallel in the feedback I
get expected results. But when I add one more resistor in series
with the above components (that are in parallel themselves), the
output voltage increases by factor of 1000. I did the math and
solved the problem analytically and it does not support such an
increase in Vout.

Did anybody have such problems? Or does anybody have an idea why
this may happen? I would appreciate any advise.

I already tried changing time step interval.

Thank you,

edgar
univ hawaii
usa
 
On Mon, 26 Apr 2004 23:49:30 -1000, the renowned "Edgar Y.
Lobachevskiy" <lobachev@hawaii.edu> wrote:

Hi all:

I am running a simulation on basic integrator using PROTEL. when I
have a bleeding resistor and capacitor in parallel in the feedback I
get expected results. But when I add one more resistor in series
with the above components (that are in parallel themselves), the
output voltage increases by factor of 1000. I did the math and
solved the problem analytically and it does not support such an
increase in Vout.
What do you mean that it "increases by a factor of 1000"? The initial
voltage or the slope? What's the initial voltage across the capacitor?
What are the component values?

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
 
Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote:

On Mon, 26 Apr 2004 23:49:30 -1000, the renowned "Edgar Y.
Lobachevskiy" <lobachev@hawaii.edu> wrote:



Hi all:

I am running a simulation on basic integrator using PROTEL. when I
have a bleeding resistor and capacitor in parallel in the feedback I
get expected results. But when I add one more resistor in series
with the above components (that are in parallel themselves), the
output voltage increases by factor of 1000. I did the math and
solved the problem analytically and it does not support such an
increase in Vout.

What do you mean that it "increases by a factor of 1000"? The initial
voltage or the slope? What's the initial voltage across the capacitor?
What are the component values?
Better still, how about a schematic (in
alt.binaries.schematics.electronic or on a web page, or in ASCII.)

--
Terry Pinnell
Hobbyist, West Sussex, UK
 
When I said 'increases by factor 1000' I meant that if the voltage without
the series resistor was 50mV, then with the addition of 100K resistor in
series, Vout jumps to 50V. My analytical derivation does not support 50V at
Vout. I submitted another post with the circuit of the opamp in
alt.binaries.schematics.electronics under OPAMP SIMULATION AND PROTEL
subject. Please let me know what you think of the discrepancy and if it can
be verified.

edgar
unv hawaii
usa



"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message
news:qvcs80pe96skrmj6o8cupelolqik23ekcf@4ax.com...
On Mon, 26 Apr 2004 23:49:30 -1000, the renowned "Edgar Y.
Lobachevskiy" <lobachev@hawaii.edu> wrote:



Hi all:

I am running a simulation on basic integrator using PROTEL. when I
have a bleeding resistor and capacitor in parallel in the feedback I
get expected results. But when I add one more resistor in series
with the above components (that are in parallel themselves), the
output voltage increases by factor of 1000. I did the math and
solved the problem analytically and it does not support such an
increase in Vout.

What do you mean that it "increases by a factor of 1000"? The initial
voltage or the slope? What's the initial voltage across the capacitor?
What are the component values?

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers:
http://www.trexon.com
Embedded software/hardware/analog Info for designers:
http://www.speff.com
 
Edgar Y. Lobachevskiy wrote:
When I said 'increases by factor 1000' I meant that if the voltage without
the series resistor was 50mV, then with the addition of 100K resistor in
series, Vout jumps to 50V. My analytical derivation does not support 50V at
Vout. I submitted another post with the circuit of the opamp in
alt.binaries.schematics.electronics under OPAMP SIMULATION AND PROTEL
subject. Please let me know what you think of the discrepancy and if it can
be verified.

edgar
unv hawaii
usa



"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> wrote in message
news:qvcs80pe96skrmj6o8cupelolqik23ekcf@4ax.com...

On Mon, 26 Apr 2004 23:49:30 -1000, the renowned "Edgar Y.
Lobachevskiy" <lobachev@hawaii.edu> wrote:



Hi all:

I am running a simulation on basic integrator using PROTEL. when I
have a bleeding resistor and capacitor in parallel in the feedback I
get expected results. But when I add one more resistor in series
with the above components (that are in parallel themselves), the
output voltage increases by factor of 1000. I did the math and
solved the problem analytically and it does not support such an
increase in Vout.

What do you mean that it "increases by a factor of 1000"? The initial
voltage or the slope? What's the initial voltage across the capacitor?
What are the component values?

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers:

http://www.trexon.com

Embedded software/hardware/analog Info for designers:

http://www.speff.com


What version of Protel? Why not ask on the Protel group??
 
Terry Pinnell <terrypin@dial.pipex.com> wrote:

Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote:

On Mon, 26 Apr 2004 23:49:30 -1000, the renowned "Edgar Y.
Lobachevskiy" <lobachev@hawaii.edu> wrote:



Hi all:

I am running a simulation on basic integrator using PROTEL. when I
have a bleeding resistor and capacitor in parallel in the feedback I
get expected results. But when I add one more resistor in series
with the above components (that are in parallel themselves), the
output voltage increases by factor of 1000. I did the math and
solved the problem analytically and it does not support such an
increase in Vout.

What do you mean that it "increases by a factor of 1000"? The initial
voltage or the slope? What's the initial voltage across the capacitor?
What are the component values?

Better still, how about a schematic (in
alt.binaries.schematics.electronic or on a web page, or in ASCII.)
Thanks for the emailed schematic. (BTW, your 180KB JPG file can be
reduced to about 7KB if changed to a b/w, cropped GIF.) I gather you
simultaneously posted this to alt.binaries.schematics.electronic, but
I don't see it here.

Anyway, I don't think the schematic and subsequent output waveforms
you sent really make your problem any clearer. And there appear to be
inconsistencies between those and your original description. Pending
discussion here (or in alt.binaries.schematics.electronic), I've
emailed a reply.

--
Terry Pinnell
Hobbyist, West Sussex, UK
 

Welcome to EDABoard.com

Sponsor

Back
Top