One Simple Question

[Naimesh]

Pls tell which is the better way of the two.


I have a SPARTAN II based design. there is serial output from the FPGA

which a uP will read. Clock for the serial (say RXC (output of FPGA))

output is divided by 16 clock of the master clock (say clk16x(input to

the FPGA)). FPGA will change the data on the positive edge of the RXC

and uP will read the data on the negative edge of the RXC.

There were two method I could think of to implement this.

Method 1

------------------------------------------------------

process(RXC,rst)

begin

if (rst = '1') then
OP <= '0';
elsif(RXC = '1' and RXC 'event) then

OP <= IPREG(7);
IPREG = IPREG(6 downto 0) & DATA_I;
end if;

end process;

-----------------------------------------------------

Method 2

-----------------------------------------------------

process(clk16x,rst)

begin

if(rst = '1') then
RXC0 = '0';
RXC1 = '0';
elsif (clk16x = '1' and clk16x 'event) then

RXC0 <= RXC;
RXC1 <= RXC0;
end if;

end process;

process(clk16x,rst)

begin

if (rst = '1') then
OP <= '0';
elsif(clk16x = '1' and clk16x 'event) then
if(RXC0 = '1' and RXC1 '0') then
OP <= IPREG(7);
IPREG = IPREG(6 downto 0) & DATA_I;
end if;
end if;

end process;

---------------------------------------------------------------
I dont have much experience in vhdl but have heard that you should not
use two clocks. that directly suggest use second method. Problem is in
second method ouput data will change two clk16x cycles after the
positve edge of the RXC. First positve edge after clk16x to update
RXC0 and RXC1 and seond edge of clk16x to give actual oupput.

which is the better method? any third one better than both?

RXC is 1.544 MHz

 

[Jerker Hammarberg (DST)]

If I understand you correctly, the clock divider that produces RXC from
clk16x is in the same FPGA as the serial transceiver. In that case, the
clock divider can also produce a signal that will be '1' just before RXC's
falling edge, and '0' otherwise. Here's an example:

constant CLOCK_SCALE : integer := 16;
signal clock_count : integer range 0 to CLOCK_SCLAE - 1;
signal rxc_falling : std_logic;

-- Clock divider process
process (clk16x, rst)
begin
if rst = '1' then
clock_count <= '0';
rxc <= '0';
elsif clk16x'event and clk16x = '1' then
if clock_count = 0 then
clock_count <= CLOCK_SCALE;
rxc <= '1';
elsif clock_count = CLOCK_SCALE / 2 then
clock_count <= CLOCK_SCALE / 2 - 1;
rxc <= '0';
else
clock_count <= clock_count - 1;
end if;
end if;
end process;

-- Signal falling edge to transceive process
rxc_falling <= '1' when clock_count = CLOCK_SCALE / 2 else '0';

-- Transceive process
process (clk16x, rst)
begin
if rst = '1' then
-- Reset
elsif clk16x'event and clk16x = '1' then
if rxc_falling = '1' then
-- Shift input/output registers
end if;
end if;
end process;

 

[Naimesh]

"Jerker Hammarberg \(DST\)" <jerkerNO@SPAMdst.se> wrote in message news:<40e55576$1_1@read01.nntp.se.dataphone.net>...

If I understand you correctly, the clock divider that produces RXC from
clk16x is in the same FPGA as the serial transceiver. In that case, the
clock divider can also produce a signal that will be '1' just before RXC's
falling edge, and '0' otherwise. Here's an example:

=====

yes, RXC generator from clk16x is in the same FPGA and I could get
that signal rxcedge. Because of this my delay of the output will now
be 1 clk16x cycle rather than 2 clk16x cycles. As clk16x is 16 times
faster than RXC I think 1 clk16x should not be a problem. Thanks for
the suggestion..

Just for curiosity which is the better method? to use signal like
clkedge or give the derived clock to the flip flop..

Naimesh

 

[Jerker Hammarberg (DST)]

yes, RXC generator from clk16x is in the same FPGA and I could get
that signal rxcedge. Because of this my delay of the output will now
be 1 clk16x cycle rather than 2 clk16x cycles. As clk16x is 16 times
faster than RXC I think 1 clk16x should not be a problem. Thanks for
the suggestion..

You should be able to make it with no delay at all! Notice that the rxcedge
signal is '1' the cycle BEFORE the falling edge of RXC. On the rising edge
of clk16x that follows, the RXC generator will set RXC <= '0' and the
trensceiver process will shift its register - both at the same time. The
example I provided works like that.

Just for curiosity which is the better method? to use signal like
clkedge or give the derived clock to the flip flop..

Well, personally I always try to avoid multiple clocks since it's always a
headache to ensure that the signals between flip-flops on different clocks
are stable in time. So I would clearly use the clkedge signal. But for
someone who's experienced in using multiple clocks (unlike me), it might be
an option to use RXC as a second clock. After all, the code becomes clearer
and more compact. So to answer you question, I guess it's a matter of
personal taste!

/Jerker