One Second Pulse-Width, Once Per Hour

[Jim Thompson]

I can't locate the original post, but there was a request for a way to
generate a one second pulse-width, occurring once per hour. I
happened on to a similar circuit in the 74HC4040 data sheet and
modified it for the required pulse-width.

It is posted on the S.E.D/Schematic Page of my website as...

"OneSecPulseWidthOncePerHour.pdf"

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Al Borowski]

Jim Thompson wrote:

I can't locate the original post, but there was a request for a way to
generate a one second pulse-width, occurring once per hour. I
happened on to a similar circuit in the 74HC4040 data sheet and
modified it for the required pulse-width.

This is just *begging* for a low end PIC

This would take literally 5 mins to code (if that) and be very accurate.
Only problem is if the OP doesn't have a programmer. If he does, heck,
I'll even code it.

Al

 

[Winfield Hill]

Tom Del Rosso wrote...

Jim Thompson typed:
I can't locate the original post, but there was a request for a
way to generate a one second pulse-width, occurring once per hour.
I happened on to a similar circuit in the 74HC4040 data sheet and
modified it for the required pulse-width.

It is posted on the S.E.D/Schematic Page of my website as...
"OneSecPulseWidthOncePerHour.pdf"

Jim's circuit actually gives a one-second pulse every 30 minutes.
That's because the high-order stage goes through only half a cycle;
the 2^12 stage goes high after 2^11 seconds. The 2^5 connection is
OK, but the three 2^10 to 2^12-stage connections must be incremented.
Fortunately the necessary stages are available on the 4020 chip type.

Aren't there 2 race conditions?

If the flipflop output drove the counter reset that would fix one.
(Possible runt clock pulse.)

The clock/reset pulse is about a dozen logic delays long, because
of the ripple-counter's delays, so it will work in that respect.

However, I prefer synchronously clocking the output flipflop, which
is more accurate (*exactly* 1 second) and reduces the IC count. A
single octal logic gate (hc30 or cd4048) decodes the required 3599
count for the flipflop's D input, and no inverters are necessary.

Another pleasant choice is the elegant little RED3600 divider from
LSI Computer: This means yet one fewer IC, and a miniDIP at that!
http://www.lsicsi.com/ http://www.lsicsi.com/pdfs/RED_SERIES.pdf

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Fred Bloggs]

Tom Del Rosso wrote:

In news:k7km60500omujl232ldhqh9cri4tc25pnj@4ax.com,
Jim Thompson typed:

I can't locate the original post, but there was a request for a way to
generate a one second pulse-width, occurring once per hour. I
happened on to a similar circuit in the 74HC4040 data sheet and
modified it for the required pulse-width.

It is posted on the S.E.D/Schematic Page of my website as...

"OneSecPulseWidthOncePerHour.pdf"


Aren't there 2 race conditions?

If the flipflop output drove the counter reset that would fix one.
(Possible runt clock pulse.)

If the flipflop set and clear were used instead of the clock input that
would fix the other. (Clock rises right after clear goes false.)

The critical timing parameters for this circuit are the minimum CP width
and the CLR removal time for the 74HC74, and minimum MR width for the
4040. Minimum CP is on the order of the family gate delay, and the
circuit maintains CP for three delays: HC4040 MR->Qn->HC20->HC04. The
CLR removal time is the minimum time HC74 CLR must be removed to
guarantee the FF will receive the CP clock positive edge- the
requirement here is a very brief time 5ns, on the order of 1/3 gate
delay. The circuit margin here is even greater, being the HC20 gate
delay plus the HC4040 ripple counter delay from Q1 to the least bit
detected by the HC20 which is about 4ns per stage. The minimum MR
duration will be three gate delays: HC4040 MR->Qn, HC20, and HC04. So
that overall, the worst-case timing margin is two macro gate delays,
making allowance for worst case transition times on the order of a
single gate delay. The circuit will work reliably under all
environmental operating conditions.

 

[Fred Bloggs]

Winfield Hill wrote:

Tom Del Rosso wrote...

Jim Thompson typed:

I can't locate the original post, but there was a request for a
way to generate a one second pulse-width, occurring once per hour.
I happened on to a similar circuit in the 74HC4040 data sheet and
modified it for the required pulse-width.

It is posted on the S.E.D/Schematic Page of my website as...
"OneSecPulseWidthOncePerHour.pdf"


Jim's circuit actually gives a one-second pulse every 30 minutes.
That's because the high-order stage goes through only half a cycle;
the 2^12 stage goes high after 2^11 seconds. The 2^5 connection is
OK, but the three 2^10 to 2^12-stage connections must be incremented.
Fortunately the necessary stages are available on the 4020 chip type.

The circuit decodes a 3600 count of 1Hz CLK- this is ONE hour. The
timing is exactly synchronous with the negative going clock edge and the
timing accuracy is within 50ppb.

 

[Jim Thompson]

On 1 Apr 2004 04:14:50 -0800, Winfield Hill
<Winfield_member@newsguy.com> wrote:

Tom Del Rosso wrote...

Jim Thompson typed:
I can't locate the original post, but there was a request for a
way to generate a one second pulse-width, occurring once per hour.
I happened on to a similar circuit in the 74HC4040 data sheet and
modified it for the required pulse-width.

It is posted on the S.E.D/Schematic Page of my website as...
"OneSecPulseWidthOncePerHour.pdf"

Jim's circuit actually gives a one-second pulse every 30 minutes.
That's because the high-order stage goes through only half a cycle;
the 2^12 stage goes high after 2^11 seconds. The 2^5 connection is
OK, but the three 2^10 to 2^12-stage connections must be incremented.
Fortunately the necessary stages are available on the 4020 chip type.

Win, Your brain must be slipping. Time for some VetaVitaVegamin ?

Aren't there 2 race conditions?

No.

81ns from clock edge to reset pulse.

20ns until reset is accomplished internal to the 4040.

Reset pulse is 46ns long.

If the flipflop output drove the counter reset that would fix one.
(Possible runt clock pulse.)

The clock/reset pulse is about a dozen logic delays long, because
of the ripple-counter's delays, so it will work in that respect.

However, I prefer synchronously clocking the output flipflop, which
is more accurate (*exactly* 1 second) and reduces the IC count.

"*exactly*" ???? Give me a break. But the measured one second in my
circuit is just 53ns shy of an exact second in width; and occurs
*exactly* once per hour.

A
single octal logic gate (hc30 or cd4048) decodes the required 3599
count for the flipflop's D input, and no inverters are necessary.

Another pleasant choice is the elegant little RED3600 divider from
LSI Computer: This means yet one fewer IC, and a miniDIP at that!
http://www.lsicsi.com/ http://www.lsicsi.com/pdfs/RED_SERIES.pdf

Thanks,
- Win

Everyone wants junk-box parts... I use junk-box parts and then you
recommend a single-source specialty part ???

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[John Woodgate]

I read in sci.electronics.design that Jim Thompson
<thegreatone@example.com> wrote (in <6vbo601k49uu7961fnj6qf4t7vvqfo826m@
4ax.com&gt about 'One Second Pulse-Width, Once Per Hour', on Thu, 1 Apr
2004:

But the measured one second in my
circuit is just 53ns shy of an exact second in width;

That's a whole 53 feet at the speed of light!
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

 

[Jim Thompson]

On Thu, 1 Apr 2004 16:41:46 +0100, John Woodgate
<jmw@jmwa.demon.contraspam.yuk> wrote:

I read in sci.electronics.design that Jim Thompson
thegreatone@example.com> wrote (in <6vbo601k49uu7961fnj6qf4t7vvqfo826m@
4ax.com&gt about 'One Second Pulse-Width, Once Per Hour', on Thu, 1 Apr
2004:
But the measured one second in my
circuit is just 53ns shy of an exact second in width;

That's a whole 53 feet at the speed of light!

IIRC (I can't seem to find the OP) the requirement was a one second
pulse to drive a relay. I do think that a relay won't mind that it's
53ns short ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Fred Bloggs]

John Woodgate wrote:

I read in sci.electronics.design that Jim Thompson
thegreatone@example.com> wrote (in <6vbo601k49uu7961fnj6qf4t7vvqfo826m@
4ax.com&gt about 'One Second Pulse-Width, Once Per Hour', on Thu, 1 Apr
2004:

But the measured one second in my
circuit is just 53ns shy of an exact second in width;


That's a whole 53 feet at the speed of light!

That would be 53 feet out of 186,000 mile span?

 

[Chris Carlen]

Jim Thompson wrote:

On Thu, 1 Apr 2004 16:41:46 +0100, John Woodgate
jmw@jmwa.demon.contraspam.yuk> wrote:


I read in sci.electronics.design that Jim Thompson
thegreatone@example.com> wrote (in <6vbo601k49uu7961fnj6qf4t7vvqfo826m@
4ax.com&gt about 'One Second Pulse-Width, Once Per Hour', on Thu, 1 Apr
2004:

But the measured one second in my
circuit is just 53ns shy of an exact second in width;

That's a whole 53 feet at the speed of light!


IIRC (I can't seem to find the OP) the requirement was a one second
pulse to drive a relay. I do think that a relay won't mind that it's
53ns short ;-)

...Jim Thompson

That's not the point. The stuff switched by the relay might.


;-D


--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[Jim Thompson]

On Thu, 01 Apr 2004 09:42:25 -0800, Chris Carlen
<crcarle@BOGUS.sandia.gov> wrote:

Jim Thompson wrote:
On Thu, 1 Apr 2004 16:41:46 +0100, John Woodgate
[snip]
IIRC (I can't seem to find the OP) the requirement was a one second
pulse to drive a relay. I do think that a relay won't mind that it's
53ns short ;-)

...Jim Thompson


That's not the point. The stuff switched by the relay might.


;-D

Lame attempt at jocularity noted ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Winfield Hill]

Jim Thompson wrote...

On 1 Apr 2004 04:14:50 -0800, Winfield Hill
Winfield_member@newsguy.com> wrote:

Tom Del Rosso wrote...

Jim Thompson typed:
I can't locate the original post, but there was a request for a
way to generate a one second pulse-width, occurring once per hour.
I happened on to a similar circuit in the 74HC4040 data sheet and
modified it for the required pulse-width.

It is posted on the S.E.D/Schematic Page of my website as...
"OneSecPulseWidthOncePerHour.pdf"

Jim's circuit actually gives a one-second pulse every 30 minutes.
That's because the high-order stage goes through only half a cycle;
the 2^12 stage goes high after 2^11 seconds. The 2^5 connection is
OK, but the three 2^10 to 2^12-stage connections must be incremented.
Fortunately the necessary stages are available on the 4020 chip type.

Win, Your brain must be slipping. Time for some VetaVitaVegamin ?

Sheesh! You're right, I must be slipping, 2^11 = 2048, I knew that!

However, I prefer synchronously clocking the output flipflop, which
is more accurate (*exactly* 1 second) and reduces the IC count.

"*exactly*" ???? Give me a break. But the measured one second in
my circuit is just 53ns shy of an exact second in width; and occurs
*exactly* once per hour.

Certainly your pulse starts at 1-hour intervals, but it's the one-
second duration that suffers. The ripple delay spec is 1160ns max
for a CD4040 to Q5 (with 50pF load), and 63 + 4*38 = 215ns for an
HC4040 (from the Motorola data sheet), compared to 63ns for the Q1
output delay. Sure 152ns max isn't much, but it's more than zero
(i.e. equal delays hi- and lo-going) for my preferred synchronous
connection. (I used to design battery-powered instruments where
sub-microsecond cmos delays in this type of timing circuit *did*
matter... hmm, that was in 1969, and no 'HC parts were available.)

Hey, what about my preferred synchronous connection also saving on
the parts count, isn't that important anymore? Doesn't that count?

A single octal logic gate (hc30 or cd4048) decodes the required 3599
count for the flipflop's D input, and no inverters are necessary.

Another pleasant choice is the elegant little RED3600 divider from
LSI Computer: This means yet one fewer IC, and a miniDIP at that!
http://www.lsicsi.com/ http://www.lsicsi.com/pdfs/RED_SERIES.pdf

Everyone wants junk-box parts... I use junk-box parts and then you
recommend a single-source specialty part ???

Yep, some junk boxes are better equipped than others - I have the
cool RED60 and RED3600 parts in mine! Besides, I'm sure you don't
mind my mentioning elegant exotic parts if they're reasonably easy
to get: Gemini Electronic Components, Valhalla, NY (800) 882-6414.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Jim Thompson]

On 1 Apr 2004 12:37:12 -0800, Winfield Hill
<Winfield_member@newsguy.com> wrote:

Jim Thompson wrote...

[snip]

Win, Your brain must be slipping. Time for some VetaVitaVegamin ?

Do you remember the VetaVitaVegamin skit that Lucille Ball did eons
ago ?

Sheesh! You're right, I must be slipping, 2^11 = 2048, I knew that!

However, I prefer synchronously clocking the output flipflop, which
is more accurate (*exactly* 1 second) and reduces the IC count.

"*exactly*" ???? Give me a break. But the measured one second in
my circuit is just 53ns shy of an exact second in width; and occurs
*exactly* once per hour.

Certainly your pulse starts at 1-hour intervals, but it's the one-
second duration that suffers. The ripple delay spec is 1160ns max
for a CD4040 to Q5 (with 50pF load), and 63 + 4*38 = 215ns for an
HC4040 (from the Motorola data sheet), compared to 63ns for the Q1
output delay. Sure 152ns max isn't much, but it's more than zero
(i.e. equal delays hi- and lo-going) for my preferred synchronous
connection. (I used to design battery-powered instruments where
sub-microsecond cmos delays in this type of timing circuit *did*
matter... hmm, that was in 1969, and no 'HC parts were available.)

Hey, what about my preferred synchronous connection also saving on
the parts count, isn't that important anymore? Doesn't that count?

A single octal logic gate (hc30 or cd4048) decodes the required 3599
count for the flipflop's D input, and no inverters are necessary.

Another pleasant choice is the elegant little RED3600 divider from
LSI Computer: This means yet one fewer IC, and a miniDIP at that!
http://www.lsicsi.com/ http://www.lsicsi.com/pdfs/RED_SERIES.pdf

Everyone wants junk-box parts... I use junk-box parts and then you
recommend a single-source specialty part ???

Yep, some junk boxes are better equipped than others - I have the
cool RED60 and RED3600 parts in mine! Besides, I'm sure you don't
mind my mentioning elegant exotic parts if they're reasonably easy
to get: Gemini Electronic Components, Valhalla, NY (800) 882-6414.

Thanks,
- Win

whill_at_picovolt-dot-com

I personally wouldn't use the 4040, I'd use something in the 'HC160
family, but that requires thinking about pre-loading, etc., something
I couldn't manage after a nice wine luncheon with my wife, celebrating
our 44th Anniversary ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Winfield Hill]

Jim Thompson wrote...

Win, Your brain must be slipping. Time for some VetaVitaVegamin ?

Do you remember the VetaVitaVegamin skit that Lucille Ball did eons
ago ?

Yes, now that you mention it, but only from having seen it in
re-runs, that I'll admit to. :&gt

I personally wouldn't use the 4040, I'd use something in the 'HC160
family, but that requires thinking about pre-loading, etc.,

Yep, full synchronous is the way to go, but with '160 you're up two
more in the chip count. These days we turn to PLDs for this stuff:
everything in one chip. Or a uP, if timing accuracy doesn't matter.

This means we just show a box with some wires going in and out, and
specify that the programming is left as an exercise for the reader.

... something I couldn't manage after a nice wine luncheon with
my wife, celebrating our 44th Anniversary ;-)

Congrats all round, of course! Lesseee, was she a teenage bride?

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Jim Thompson]

On 1 Apr 2004 14:03:58 -0800, Winfield Hill
<Winfield_member@newsguy.com> wrote:

Jim Thompson wrote...

[snip]

... something I couldn't manage after a nice wine luncheon with
my wife, celebrating our 44th Anniversary ;-)

Congrats all round, of course! Lesseee, was she a teenage bride?

Thanks,
- Win

whill_at_picovolt-dot-com

Yep, one of those marriages that wasn't supposed to last, I was 20,
"N" was 18. (And I was still a Sophomore at MIT.)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[John Fields]

On 1 Apr 2004 14:03:58 -0800, Winfield Hill
<Winfield_member@newsguy.com> wrote:

Jim Thompson wrote...

Win, Your brain must be slipping. Time for some VetaVitaVegamin ?

Do you remember the VetaVitaVegamin skit that Lucille Ball did eons
ago ?

Yes, now that you mention it, but only from having seen it in
re-runs, that I'll admit to. :&gt

I personally wouldn't use the 4040, I'd use something in the 'HC160
family, but that requires thinking about pre-loading, etc.,

---
Puhleeezeee!!!

For simple stuff, you've got 12 bits to work with with a 4040, and
four with a 160. One chip against three... it's like golf, the
smaller number wins.
---

Yep, full synchronous is the way to go, but with '160 you're up two
more in the chip count. These days we turn to PLDs for this stuff:
everything in one chip. Or a uP, if timing accuracy doesn't matter.

---
Well Win, it seems that you don't know that "these days" all _we_ have
to do is count the number of clocks you need to get the accuracy you
want and then subtract the number of cycles it takes to execute the
instructions to make everything come out just right. You're welcome.
---

This means we just show a box with some wires going in and out, and
specify that the programming is left as an exercise for the reader.

---
Sometimes, the knowing "exercise left for the reader" phrase means
that we don't know how to do it either...
---

--
John Fields

 

[Spehro Pefhany]

On 1 Apr 2004 14:03:58 -0800, the renowned Winfield Hill
<Winfield_member@newsguy.com> wrote:

Yep, full synchronous is the way to go, but with '160 you're up two
more in the chip count. These days we turn to PLDs for this stuff:
everything in one chip. Or a uP, if timing accuracy doesn't matter.

You shouldn't assume that uP's are only useful if timing doesn't
matter. I just did a uP generating 5 frequencies simultaneously (in
the low kHz to high hundreds of Hz) with NO jitter (for some of us
anyway, I'm sure JL would see scads of jitter as the xtal oscillator
jitters a bit) and frequency resolution of one clock cycle. Of course
that's using peripheral hardware on the chip, but on the plus side,
it's ALL on the chip.

This means we just show a box with some wires going in and out, and
specify that the programming is left as an exercise for the reader.

Teeeeedyusss.

... something I couldn't manage after a nice wine luncheon with
my wife, celebrating our 44th Anniversary ;-)

Congrats all round, of course! Lesseee, was she a teenage bride?

Indeed. Congratulations. We're only 1/3 of the way there. ;-)

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Winfield Hill]

John Fields wrote...

Winfield Hill wrote:

Or a uP, if timing accuracy doesn't matter.

Well Win, it seems that you don't know that "these days" all
_we_ have to do is count the number of clocks you need to get
the accuracy you want and then subtract the number of cycles
it takes to execute the instructions to make everything come
out just right. You're welcome.

I knew that! Having done it myself, but forgotten. Sheesh!

Thanks,
- Win

whill_at_picovolt-dot-com

 

[GPG]

Jim Thompson <thegreatone@example.com> wrote in message news:<k7km60500omujl232ldhqh9cri4tc25pnj@4ax.com>...

I can't locate the original post, but there was a request for a way to
http://groups.google.com/groups?dq=&hl=en&lr=&ie=UTF-8&threadm=Dt-dnd1LfJja1vbdRVn-vw%40comcast.com&prev=/groups%3Fdq%3D%26num%3D25%26hl%3Den%26lr%3D%26ie%3DUTF-8%26group%3Dsci.electronics.design%26start%3D25

and
http://groups.google.com/groups?dq=&hl=en&lr=&ie=UTF-8&threadm=BC8E2238.43EF%25davidwcole%40earthlink.net&prev=/groups%3Fdq%3D%26num%3D25%26hl%3Den%26lr%3D%26ie%3DUTF-8%26group%3Dsci.electronics.design%26start%3D75
and
http://groups.google.com/groups?dq=&hl=en&lr=&ie=UTF-8&threadm=62069f15.0403261959.521b4394%40posting.google.com&prev=/groups%3Fdq%3D%26num%3D25%26hl%3Den%26lr%3D%26ie%3DUTF-8%26group%3Dsci.electronics.design%26start%3D125
and
http://groups.google.com/groups?dq=&hl=en&lr=&ie=UTF-8&threadm=406C3AFF.8090306%40nospam.com&prev=/groups%3Fhl%3Den%26lr%3D%26ie%3DUTF-8%26group%3Dsci.electronics.design

 

[Tam/WB2TT]

Actually, you can have the best of two worlds by putting the Dff inside the
feedback loop. Might as well take advantage of the fact that HC74s come in
pairs (prevents having to decode an odd number). Here is how:

1. delete the hc04.
2. connect the hc20 output to D of first hc74
3. connect Q of first hc74 to D of second hc74
5. decode 3558
6. connect all clock inputs together.
7. connect Q* of second hc74 to RESET of hc4020
8. connect Q of second hc74 to SET of first hc74

Tam

"Jim Thompson" <thegreatone@example.com> wrote in message
news:8e1p60tkc3c5jdcm38ld96pge3s14gs2ef@4ax.com...

On 1 Apr 2004 12:37:12 -0800, Winfield Hill
Winfield_member@newsguy.com> wrote:

Jim Thompson wrote...

[snip]

Win, Your brain must be slipping. Time for some VetaVitaVegamin ?

Do you remember the VetaVitaVegamin skit that Lucille Ball did eons
ago ?


Sheesh! You're right, I must be slipping, 2^11 = 2048, I knew that!

However, I prefer synchronously clocking the output flipflop, which
is more accurate (*exactly* 1 second) and reduces the IC count.

"*exactly*" ???? Give me a break. But the measured one second in
my circuit is just 53ns shy of an exact second in width; and occurs
*exactly* once per hour.

Certainly your pulse starts at 1-hour intervals, but it's the one-
second duration that suffers. The ripple delay spec is 1160ns max
for a CD4040 to Q5 (with 50pF load), and 63 + 4*38 = 215ns for an
HC4040 (from the Motorola data sheet), compared to 63ns for the Q1
output delay. Sure 152ns max isn't much, but it's more than zero
(i.e. equal delays hi- and lo-going) for my preferred synchronous
connection. (I used to design battery-powered instruments where
sub-microsecond cmos delays in this type of timing circuit *did*
matter... hmm, that was in 1969, and no 'HC parts were available.)

Hey, what about my preferred synchronous connection also saving on
the parts count, isn't that important anymore? Doesn't that count?

A single octal logic gate (hc30 or cd4048) decodes the required 3599
count for the flipflop's D input, and no inverters are necessary.

Another pleasant choice is the elegant little RED3600 divider from
LSI Computer: This means yet one fewer IC, and a miniDIP at that!
http://www.lsicsi.com/ http://www.lsicsi.com/pdfs/RED_SERIES.pdf

Everyone wants junk-box parts... I use junk-box parts and then you
recommend a single-source specialty part ???

Yep, some junk boxes are better equipped than others - I have the
cool RED60 and RED3600 parts in mine! Besides, I'm sure you don't
mind my mentioning elegant exotic parts if they're reasonably easy
to get: Gemini Electronic Components, Valhalla, NY (800) 882-6414.

Thanks,
- Win

whill_at_picovolt-dot-com

I personally wouldn't use the 4040, I'd use something in the 'HC160
family, but that requires thinking about pre-loading, etc., something
I couldn't manage after a nice wine luncheon with my wife, celebrating
our 44th Anniversary ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.