One or more signals are missing in the sensitivity list of a

[$B$J$J$7$H$/$a$$(B]

Hi experts.
I'm really new to Verilog and digital circuit.(and english)
I'm studying Verilog now and trying to design a module that will receive data in LVDS.
the following is my code.
When I synthesised this, I received the following Warning message.

************************************************************************
WARNING:Xst:905 - "LVDS_Rcv.v" line 46: One or more signals are missing in the sensitivity list of always block.
To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list.
Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<DATA1>, <DATA2>, <cnt>, <regClkcnt>
************************************************************************

i need to capture data1 and data2 signal at both the posedge and negedge of CLK.
and I also need to reset the module when RST is signaled.
so i believe that i have listed all signals that is necessary for my always block.
why synthesizer gives me the message?
could you tell me the reason and how to get rid of it?
thanks.


************************************************************************
`timescale 1ns / 1ps
module LVDS_Rcv(RST, CLK, DATA1, DATA2, OE, RCVDATA, CLKCNT);
input RST;
input CLK;
input DATA1;
input DATA2;
output OE;
output [15:0] RCVDATA;
output [15:0] CLKCNT;

reg [3:0] cnt;
reg [15:0] regRcvData;
reg [15:0] regClkcnt;
always @(CLK or RST) // both edge of CLK, i need to capture data1 and data2.
begin
if(RST)
begin
regRcvData <= 0;
cnt <= 4'b0000;
regRcvData <= 0;
regClkcnt <= 0;
end
else
begin
// push 2bits into register
regRcvData <= {regRcvData[13:0], DATA1, DATA2};

if(cnt == 4'b1000) cnt <= 0;
else cnt <= cnt + 1;

if(regClkcnt == 16'hFFFF) regClkcnt <= 0;
else regClkcnt <= regClkcnt + 1;
end
end

assign OE = (cnt == 4'b1000 ? 1 : 0);
assign RCVDATA = regRcvData;
assign CLKCNT = regClkcnt;
endmodule
************************************************************************

 

[Gabor]

On 3/2/2014 7:17 AM, ななしとくめい wrote:

Hi experts.
I'm really new to Verilog and digital circuit.(and english)
I'm studying Verilog now and trying to design a module that will receive data in LVDS.
the following is my code.
When I synthesised this, I received the following Warning message.

************************************************************************
WARNING:Xst:905 - "LVDS_Rcv.v" line 46: One or more signals are missing in the sensitivity list of always block.
To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list.
Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:<DATA1>, <DATA2>, <cnt>, <regClkcnt
************************************************************************

i need to capture data1 and data2 signal at both the posedge and negedge of CLK.
and I also need to reset the module when RST is signaled.
so i believe that i have listed all signals that is necessary for my always block.
why synthesizer gives me the message?
could you tell me the reason and how to get rid of it?
thanks.


************************************************************************
`timescale 1ns / 1ps
module LVDS_Rcv(RST, CLK, DATA1, DATA2, OE, RCVDATA, CLKCNT);
input RST;
input CLK;
input DATA1;
input DATA2;
output OE;
output [15:0] RCVDATA;
output [15:0] CLKCNT;

reg [3:0] cnt;
reg [15:0] regRcvData;
reg [15:0] regClkcnt;
always @(CLK or RST) // both edge of CLK, i need to capture data1 and data2.
begin
if(RST)
begin
regRcvData <= 0;
cnt <= 4'b0000;
regRcvData <= 0;
regClkcnt <= 0;
end
else
begin
// push 2bits into register
regRcvData <= {regRcvData[13:0], DATA1, DATA2};

if(cnt == 4'b1000) cnt <= 0;
else cnt <= cnt + 1;

if(regClkcnt == 16'hFFFF) regClkcnt <= 0;
else regClkcnt <= regClkcnt + 1;
end
end

assign OE = (cnt == 4'b1000 ? 1 : 0);
assign RCVDATA = regRcvData;
assign CLKCNT = regClkcnt;
endmodule
************************************************************************

What you're trying to describe is a dual-data-rate flip-flop.
Unfortunately you can't infer these for Xilinx FPGAs. You
need to instantiate them. Find the Libraries Guide and
look for the appropriate input DDR flop for your FPGA family,
which might be something like IDDR2.

There are some Xilinx CPLD's, CoolRunner 2, that allow you to
define flops that trigger on both edges of the clock. For
these you need something like:

always @ (posedge CLK or negedge CLK or posedge RST)
if (RST) begin
<reset actions here>
end
else begin
< clocked actions here>
end

But as I said you can't do this for any of the FPGA families.
Check the language templates (light-bulb icon in ISE) or the
XST user guide for the proper syntax for clocked logic. It
always needs some sort of edge sensitivity. Any sensitivity
list with only signals and no edge keywords (posedge, negedge)
will infer combinatorial logic, or possibly gated latches for
synthesis.

--
Gabor

 

[$B$J$J$7$H$/$a$$(B]

Thanks for replying.
Thanks to your help, I can understand why the always-block gives me the message.
and I also understood that I need to go to library to find some FF for DDR.