one clock late

[Paul]

Hi

/*
always @(posedge CLK) begin
if (ACK0) ex<=1; else ex<=0; // always 1 clock later !!!!!
end
*/
always @(ACK0) begin
if (ACK0) ex<=1; else ex<=0; // syncronous !!!!!
end

I've noticed in simulation that to have "ex" and "ACK0" syncronized,
one can not use CLK as its sensitive list. Else it would happen "ex"
is always one clock late than ACK0.

I wonder how far back this behaviour was decreed? No new beginner
could forsee such behavior.

 

[Jonathan Bromley]

"Paul" <paulw@mmail.ath.cx> wrote in message
news:3ba4d769.0402020230.10a73162@posting.google.com...

No new beginner
could forsee such behavior.

Well, indeed. No new beginner could foresee
sin^2 + cos^2 = 1
either. But they're both true, and both blindingly
obvious once you've taken the trouble to study the basics.

I would be deeply worried to find the output of a
D-flipflop synchronised with its D input. Would you?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Andy Peters]

paulw@mmail.ath.cx (Paul) wrote in message news:<3ba4d769.0402020230.10a73162@posting.google.com>...

Hi

/*
always @(posedge CLK) begin
if (ACK0) ex<=1; else ex<=0; // always 1 clock later !!!!!
end
*/
always @(ACK0) begin
if (ACK0) ex<=1; else ex<=0; // syncronous !!!!!
end

I've noticed in simulation that to have "ex" and "ACK0" syncronized,
one can not use CLK as its sensitive list. Else it would happen "ex"
is always one clock late than ACK0.

I wonder how far back this behaviour was decreed? No new beginner
could forsee such behavior.

Ummmmmm...before you start blaming the language, you might consider
learning it. (Or at least learning about digital design.)

The first example is sensitive only to the rising edge of the clock --
it's a flip-flop. The second example is sensitive only to ACK0 --
it's combinatorial logic.

Here's why you see the delay on the first example. I assume that ACK0
is synchronous to CLK. In that case, ACK0 changes a delta time after
the rising edge of CLK. Of course, your waveform viewer doesn't show
this (since a delta time is infinitesmal), so here's a homework
assignment: open up your Verilog books and carefully read the sections
about the scheduler and delta delays.

The point is that since ACK0 changes slightly after the rising edge of
CLK, that change will be recognized by the ex flop on the NEXT rising
edge -- hence the one-tick delay. Of course, this exactly models a
real flip-flop with zero clock-to-out time.

The second example is sensitive to ACK0, so of course its output, ex,
changes a delta time after ACK0 changes. It's pure combinatorial
logic.

Free hint: more advanced Verilog coders will write the logic you
describe as:

always @(posedge CLK) begin
ex <= ACK0;
end

Second homework assignment: why is that better?

--a

 

[Sajan]

Well thats exactly how a flip-flop is supposed to behave.

/*********************************/
always @(posedge CLK) begin
if (ACK0) ex<=1; else ex<=0; // always 1 clock later !!!!!
end
well the above code is a flip flop.

you could as well write this as
always @(posedge CLK) begin
ex <= ACK0;
end
/**********************************/

always @(ACK0) begin
if (ACK0) ex<=1; else ex<=0; // syncronous !!!!!
end
well this code is something we call a wire
i.e tieing ACK0 and ex together.

and you could as well write this as
ex <= ACK0;

/**********************************/


Would recommend a bit brushing up of digital concepts.



Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0402020940.3758697@posting.google.com>...

paulw@mmail.ath.cx (Paul) wrote in message news:<3ba4d769.0402020230.10a73162@posting.google.com>...
Hi

/*
always @(posedge CLK) begin
if (ACK0) ex<=1; else ex<=0; // always 1 clock later !!!!!
end
*/
always @(ACK0) begin
if (ACK0) ex<=1; else ex<=0; // syncronous !!!!!
end

I've noticed in simulation that to have "ex" and "ACK0" syncronized,
one can not use CLK as its sensitive list. Else it would happen "ex"
is always one clock late than ACK0.

I wonder how far back this behaviour was decreed? No new beginner
could forsee such behavior.

Ummmmmm...before you start blaming the language, you might consider
learning it. (Or at least learning about digital design.)

The first example is sensitive only to the rising edge of the clock --
it's a flip-flop. The second example is sensitive only to ACK0 --
it's combinatorial logic.

Here's why you see the delay on the first example. I assume that ACK0
is synchronous to CLK. In that case, ACK0 changes a delta time after
the rising edge of CLK. Of course, your waveform viewer doesn't show
this (since a delta time is infinitesmal), so here's a homework
assignment: open up your Verilog books and carefully read the sections
about the scheduler and delta delays.

The point is that since ACK0 changes slightly after the rising edge of
CLK, that change will be recognized by the ex flop on the NEXT rising
edge -- hence the one-tick delay. Of course, this exactly models a
real flip-flop with zero clock-to-out time.

The second example is sensitive to ACK0, so of course its output, ex,
changes a delta time after ACK0 changes. It's pure combinatorial
logic.

Free hint: more advanced Verilog coders will write the logic you
describe as:

always @(posedge CLK) begin
ex <= ACK0;
end

Second homework assignment: why is that better?

--a

 

[glen herrmannsfeldt]

Andy Peters wrote:

(snip)

Free hint: more advanced Verilog coders will write the logic you
describe as:

always @(posedge CLK) begin
ex <= ACK0;
end

Second homework assignment: why is that better?

How about ACK0 might not be 0 or 1?

-- glen