On using multiple clock edges

Hello everyone! In a design I'm building, I have to use two different
clocks, srcclk and dstclk. Worse, I need an option (selectable while
the design is disabled) to operate at either edge of srcclk
(thankfully, I only use the rising edge of dstclk). I'm transferring
data bidirectionally, but commands come only from the srcclk-domain,
and status is not used by the srcclk-domain circuitry; so, my only
synch problem is the controls to the dstclk-domain (which are used to
synch the bidirectional data).

Worse, I actually have two srcclk-domain modules, module1 and
module2. module1 operates at posedge when module2 operates at
negedge; module1 operates at negedge when module2 operates at posedge.

What I did was design two versions of the srcclk-clocked code, one
clocked at the positive edge, the other clocked at the negative edge.
The controls and data output are then selected based on which one is
needed by the user. Something like:

/*do the foo if dothis says so*/
reg foocommand_pe, foocommand_ne;
always @(posedge clk, negedge reset_n) if(!reset_n) foocommand_pe <=
0; else begin
if(en) begin
if(dothis_pe) foocommand_pe <= 1;
else foocommand_pe <= 0; end end
always @(negedge clk, negedge reset_n) if(!reset_n) foocommand_ne <=
0; else begin
if(en) begin
if(dothis_ne) foocommand_ne <= 1;
else foocommand_ne <= 0; end end
/*merge the command*/
wire foocommand =
(edge_select == 1) ? foocommand_pe :
(edge_select == 0) ? foocommand_ne : 'bx;

Unfortunately, this means I have twice as much code as I need to
describe the design.

Can anyone please tell me:
1. ...if it is a good idea at all? I can't think of a decent way of
implementing this without adding an XOR gate to the clock, which I
would like to avoid.
2. ...if it is possible to merge both definitions into one, and
specify somehow that there are two versions, one at posedge and one at
negedge?

Thanks!