On-Chip Oscillator

[Drew]

Hello Guys,

Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I
am using Altera Max family parts. I was wondering we can program it
using VHDL? Another question I have is, How do I reduce the Rise Time
of clock output from CPLD? I need rise time of < 2ns. I need external
circuitry but not sure what?

Feedback please!
Drew

 

[Leon Heller]

"Drew" <dhruvish@gmail.com> wrote in message
news:ad2011c0.0407270952.23895c31@posting.google.com...

Hello Guys,

Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I
am using Altera Max family parts. I was wondering we can program it
using VHDL?

I vaguely remember trying something like this a few years ago by creating
two inverters and using them to implement an oscillator with a crystal and a
couple of resistors.

Leon

 

[Jim Granville]

Drew wrote:

Hello Guys,

Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I
am using Altera Max family parts. I was wondering we can program it
using VHDL?

It is possible to make ring oscillators in CPLD, using a series of
inverters. These will have wide process/vcc/temp variations, and
should ideally be started with a NAND + Reset structures, to
avoid possible stable harmonic cases.

Another question I have is, How do I reduce the Rise Time
of clock output from CPLD? I need rise time of < 2ns. I need external
circuitry but not sure what?

Most CPLDs have a choice of OP Slew rates, with slow bein used
to reduce the bounce and RFI effects.
In the FAST mode, actual speed is largely
a function of load capacitance.
What is it that requires tr < 2ns ?

-jg

 

[Drew]

jg,

My output is a clock which eventually will control A/D converter. Now,
the clock for converter needs to have < 2ns Rise Time (For faster
sampling rate, in my case 10MSamples/s) by the spec of it.

Nobody really replied to my other question, can we generate clock on
the Programmable Device (Max3032)? I want to generate 20MHz clock on
the EPLD.

Thanks,
Drew

 

[Peter Alfke]

You asked an Altera-specific question, which delayed my response just a bit

Any modern programmable device from any of the major manufacturers will give
you a 1 ns or faster rise/fall time, and we all consider 20 MHz a low
frequency. You should not have any problem with your design, just stay away
from ancient parts.
Peter Alfke, Xilinx

From: dhruvish@gmail.com (Drew)
Organization: http://groups.google.com
Newsgroups: comp.arch.fpga
Date: 30 Jul 2004 10:52:21 -0700
Subject: Re: On-Chip Oscillator

jg,

My output is a clock which eventually will control A/D converter. Now,
the clock for converter needs to have < 2ns Rise Time (For faster
sampling rate, in my case 10MSamples/s) by the spec of it.

Nobody really replied to my other question, can we generate clock on
the Programmable Device (Max3032)? I want to generate 20MHz clock on
the EPLD.

Thanks,
Drew

 

[Jim Granville]

Drew wrote:

jg,

My output is a clock which eventually will control A/D converter. Now,
the clock for converter needs to have < 2ns Rise Time (For faster
sampling rate, in my case 10MSamples/s) by the spec of it.

Just make sure you select the FAST edge option on that pin, and keep the
traces as short as possible.

Nobody really replied to my other question, can we generate clock on
the Programmable Device (Max3032)? I want to generate 20MHz clock on
the EPLD.

I thought I had. The answer is yes, it can be done, (we have done
various delay line clocks inside CPLD ) but you get low
performance.
If you are running an ADC where low noise matters,
I'd avoid the on-chip oscillator.

If you are using a CPLD with hysteresis, you can build RC oscillators,
(again, low performance) but I do not think the Altera 3032 meets that.

If you mean attach a crystal to the CPLD, that can also be done,
but again at high risk. Spurious Oscillations, 'edge fur', and incorrect
harmonics are all possible outcomes.

If you want the smallest/cheapest Xtal Oscillator for CPLD/FPGA drive,
look at
http://www.philipslogic.com/products/collateral/logic/pdf/card_74lvc1gx04.pdf

Or, you can use an oscillator module.

-jg

 

[Peter Alfke]

Do not use an on-chip oscillator (they are not stable).
Do not use an external RC, (that's better, but still not stable)
Do not use a crystal driven by a CPLD or FPGA, because it's more trouble and
problems than it is worth.
Spend a whole dollar ( or $ 1.50) and buy yourself a crystal oscillator
module and live happily ever after !
Peter Alfke

From: Jim Granville <no.spam@designtools.co.nz
Organization: TelstraClear
Newsgroups: comp.arch.fpga
Date: Sat, 31 Jul 2004 08:30:43 +1200
Subject: Re: On-Chip Oscillator

Drew wrote:
jg,

My output is a clock which eventually will control A/D converter. Now,
the clock for converter needs to have < 2ns Rise Time (For faster
sampling rate, in my case 10MSamples/s) by the spec of it.

Just make sure you select the FAST edge option on that pin, and keep the
traces as short as possible.

Nobody really replied to my other question, can we generate clock on
the Programmable Device (Max3032)? I want to generate 20MHz clock on
the EPLD.

I thought I had. The answer is yes, it can be done, (we have done
various delay line clocks inside CPLD ) but you get low
performance.
If you are running an ADC where low noise matters,
I'd avoid the on-chip oscillator.

If you are using a CPLD with hysteresis, you can build RC oscillators,
(again, low performance) but I do not think the Altera 3032 meets that.

If you mean attach a crystal to the CPLD, that can also be done,
but again at high risk. Spurious Oscillations, 'edge fur', and incorrect
harmonics are all possible outcomes.

If you want the smallest/cheapest Xtal Oscillator for CPLD/FPGA drive,
look at
http://www.philipslogic.com/products/collateral/logic/pdf/card_74lvc1gx04.pdf

Or, you can use an oscillator module.

-jg

 

[Jim Granville]

Peter Alfke wrote:

Do not use an on-chip oscillator (they are not stable).

As noted, but there are applications where that is perfectly
acceptable.

Do not use an external RC, (that's better, but still not stable)

There are also application where this is OK. Truckloads of uC
ship these days with calibrated RC Osc, that give ~2% precision.
Newer CPLDs include hysteresis, to allow 2 & 3 terminal oscillator
designs, if one wishes.

Do not use a crystal driven by a CPLD or FPGA, because it's more trouble and
problems than it is worth.
As noted.

Spend a whole dollar ( or $ 1.50) and buy yourself a crystal oscillator
module and live happily ever after !

Unless Size, Frequency, or power considerations exclude that.
I have not seen many Modules at 32Khz, for example.
Modules under around 10mA are also rare, so you can easily find
your Osc Module chews far more power than your Xilinx Coolrunner, for
example. Depends on the design, but that could be a killer.

We have tried the 74lvc1gx04 I mentioned, (Philips have a little
Eval PCB ) and it is quite impressive.
You can vary Vcc, for quite wide Freq/Power trade offs, and it
comes in a tiny SOT23 sized package.

Peter Alfke


From: Jim Granville <no.spam@designtools.co.nz
Organization: TelstraClear
Newsgroups: comp.arch.fpga
Date: Sat, 31 Jul 2004 08:30:43 +1200
Subject: Re: On-Chip Oscillator

Drew wrote:

jg,

My output is a clock which eventually will control A/D converter. Now,
the clock for converter needs to have < 2ns Rise Time (For faster
sampling rate, in my case 10MSamples/s) by the spec of it.

Just make sure you select the FAST edge option on that pin, and keep the
traces as short as possible.


Nobody really replied to my other question, can we generate clock on
the Programmable Device (Max3032)? I want to generate 20MHz clock on
the EPLD.

I thought I had. The answer is yes, it can be done, (we have done
various delay line clocks inside CPLD ) but you get low
performance.
If you are running an ADC where low noise matters,
I'd avoid the on-chip oscillator.

If you are using a CPLD with hysteresis, you can build RC oscillators,
(again, low performance) but I do not think the Altera 3032 meets that.

If you mean attach a crystal to the CPLD, that can also be done,
but again at high risk. Spurious Oscillations, 'edge fur', and incorrect
harmonics are all possible outcomes.

If you want the smallest/cheapest Xtal Oscillator for CPLD/FPGA drive,
look at
http://www.philipslogic.com/products/collateral/logic/pdf/card_74lvc1gx04.pdf

Or, you can use an oscillator module.

-jg

 

[Joe DeLaere]

dhruvish@gmail.com (Drew) wrote in message news:<ad2011c0.0407270952.23895c31@posting.google.com>...

Hello Guys,

Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I
am using Altera Max family parts. I was wondering we can program it
using VHDL? Another question I have is, How do I reduce the Rise Time
of clock output from CPLD? I need rise time of < 2ns. I need external
circuitry but not sure what?

Feedback please!
Drew

The Altera MAX II CPLD family does have a general purpose on-chip
oscillator. The on-chip oscillator is part of the User Flash Memory
block feature but is available as a general purpose clock for the core
logic or off-chip. The frequency variation on this oscillator is
between 4.6 and 7.4 MHz. See the MAX II handbook, chapter 2 page 24
and chapter 10 page 7 for more information.

http://www.altera.com/literature/lit-max2.jsp