Old 5v TTL: What does a NAND gate looped back on itself do a

T

Thomas G. Marshall

Guest
I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.

Now I guessing that it's not going to look anything like a clean
square wave, because the transition voltages would be met mighty
fast. But are the transitions monotonic? If not, does any noise goof
up which direction its transitioning when switching that fast?

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state? At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.

Thanks!
 
On Fri, 22 May 2009 07:12:03 -0700 (PDT), "Thomas G. Marshall"
<tgmforum@gmail.com> wrote:

I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.

Now I guessing that it's not going to look anything like a clean
square wave, because the transition voltages would be met mighty
fast. But are the transitions monotonic? If not, does any noise goof
up which direction its transitioning when switching that fast?

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state? At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.

Thanks!
Click to expand...
Old slow 74-type TTL had essentially one low-gain stage, 1st order
response, so a simple gate would usually stabilize at about +1.2 volts
DC. Later gen faster parts, like AS and F will probably oscillate.
HC-type CMOS parts have multiple internal stages, higher-order delay,
so usually oscillate. Early ECL (10K, 10KH) would DC stabilize too;
faster, higher gain parts (Eclips, EL, EP) will oscillate.

10K type ECL was often used as a fast amplifier. A 7400 gate can be
used as an amplifier, too.

John
 
On May 22, 9:12 am, "Thomas G. Marshall" <tgmfo...@gmail.com> wrote:
I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.

Now I guessing that it's not going to look anything like a clean
square wave, because the transition voltages would be met mighty
fast.  But are the transitions monotonic?  If not, does any noise goof
up which direction its transitioning when switching that fast?

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state?  At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.

Depends. What is the rise time in comparison to the delay? What's
Click to expand...
the loop gain? If the loop gain is high and the rise time is fast (in
comparison to the delay) it'll oscillate as you suggest. The faster
the edge rate the "squarer" the oscillation. If the device (delay) is
slow or the loop gain is low, it'll settle to a mid point, much as an
op-amp. With few exceptions, this isn't recommended though.
 
On Fri, 22 May 2009 10:03:10 -0700 (PDT), "keithw86@gmail.com"
<keithw86@gmail.com> wrote:

On May 22, 11:22 am, "Thomas G. Marshall" <tgmfo...@gmail.com> wrote:
On May 22, 11:23 am, "keith...@gmail.com" <keith...@gmail.com> wrote:



On May 22, 9:12 am, "Thomas G. Marshall" <tgmfo...@gmail.com> wrote:

I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.

Now I guessing that it's not going to look anything like a clean
square wave, because the transition voltages would be met mighty
fast.  But are the transitions monotonic?  If not, does any noise goof
up which direction its transitioning when switching that fast?

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state?  At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.

Depends.  What is the rise time in comparison to the delay?  What's
the loop gain?  If the loop gain is high and the rise time is fast (in
comparison to the delay) it'll oscillate as you suggest.  The faster
the edge rate the "squarer" the oscillation.  If the device (delay) is
slow or the loop gain is low, it'll settle to a mid point, much as an
op-amp.  With few exceptions, this isn't recommended though.

Sure, understood.  The assumption I'm making is that the gate
internals are slower than the electron propagation :) , so I'd have to
say my initial assumptions were the settling toward the mid-point.

What's electron propagation have to do with it? Again, it'll settle
to the midpoint if the loop gain is <1 at 1/delay frequency.

But I'm I'm still not entirely convinced though that there wouldn't be
some odd shape to this "curve", noise directed perhaps, that wouldn't
be what we're expecting.

If it settles in the linear region, sure, noise will be amplified.

Imagine this for 1 example:  The voltage rises near transition, get's
stuck in a mini-curve down (very small due to noise) and is then
brought back up.  If that NAND loop back happens along the time domain
more narrowly than the noise, it might be an interesting settling
point that doesn't, well, seem obvious.  OR that the gate then tries
to shift states before it's supposed to and then we see a beat
frequency between the internals and the noise or something else goofy.

If the loop gain is high it will want to oscillate and noise will push
it into oscillation. If the loop gain is <1 noise will be amplified
but it will stabilize back to the midpoint.
Click to expand...
All digital logic families have voltage gain above 1; if it didn't,
logic signals would fade away in digital systems. Whether it
oscillates or not is a control-theory issue; gates with one gain stage
are 1st order systems and tend to not oscillate; gates with multiple
gain stages are higher-order gadgets and tend to oscillate.

Old 74-series TTL and 10K ECL had gate voltage gains in the single
digits and 1st order time response (single dominant delay node inside)
so tended to be DC stable if you connected an inverter input to its
output.

A gadget can have very high gain here and still be stable; an opamp
for example.

John
 
On May 22, 11:23 am, "keith...@gmail.com" <keith...@gmail.com> wrote:
On May 22, 9:12 am, "Thomas G. Marshall" <tgmfo...@gmail.com> wrote:

I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.

Now I guessing that it's not going to look anything like a clean
square wave, because the transition voltages would be met mighty
fast.  But are the transitions monotonic?  If not, does any noise goof
up which direction its transitioning when switching that fast?

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state?  At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.

Depends.  What is the rise time in comparison to the delay?  What's
the loop gain?  If the loop gain is high and the rise time is fast (in
comparison to the delay) it'll oscillate as you suggest.  The faster
the edge rate the "squarer" the oscillation.  If the device (delay) is
slow or the loop gain is low, it'll settle to a mid point, much as an
op-amp.  With few exceptions, this isn't recommended though.
Click to expand...

Sure, understood. The assumption I'm making is that the gate
internals are slower than the electron propagation :) , so I'd have to
say my initial assumptions were the settling toward the mid-point.

But I'm I'm still not entirely convinced though that there wouldn't be
some odd shape to this "curve", noise directed perhaps, that wouldn't
be what we're expecting.

Imagine this for 1 example: The voltage rises near transition, get's
stuck in a mini-curve down (very small due to noise) and is then
brought back up. If that NAND loop back happens along the time domain
more narrowly than the noise, it might be an interesting settling
point that doesn't, well, seem obvious. OR that the gate then tries
to shift states before it's supposed to and then we see a beat
frequency between the internals and the noise or something else goofy.

Though I'm sure it's nothing more than the settling like you suggest
{shrug}. I just find it intriguing.
 
On May 22, 11:22 am, "Thomas G. Marshall" <tgmfo...@gmail.com> wrote:
On May 22, 11:23 am, "keith...@gmail.com" <keith...@gmail.com> wrote:



On May 22, 9:12 am, "Thomas G. Marshall" <tgmfo...@gmail.com> wrote:

I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.

Now I guessing that it's not going to look anything like a clean
square wave, because the transition voltages would be met mighty
fast.  But are the transitions monotonic?  If not, does any noise goof
up which direction its transitioning when switching that fast?

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state?  At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.

Depends.  What is the rise time in comparison to the delay?  What's
the loop gain?  If the loop gain is high and the rise time is fast (in
comparison to the delay) it'll oscillate as you suggest.  The faster
the edge rate the "squarer" the oscillation.  If the device (delay) is
slow or the loop gain is low, it'll settle to a mid point, much as an
op-amp.  With few exceptions, this isn't recommended though.

Sure, understood.  The assumption I'm making is that the gate
internals are slower than the electron propagation :) , so I'd have to
say my initial assumptions were the settling toward the mid-point.
Click to expand...
What's electron propagation have to do with it? Again, it'll settle
to the midpoint if the loop gain is <1 at 1/delay frequency.

But I'm I'm still not entirely convinced though that there wouldn't be
some odd shape to this "curve", noise directed perhaps, that wouldn't
be what we're expecting.
Click to expand...
If it settles in the linear region, sure, noise will be amplified.

Imagine this for 1 example:  The voltage rises near transition, get's
stuck in a mini-curve down (very small due to noise) and is then
brought back up.  If that NAND loop back happens along the time domain
more narrowly than the noise, it might be an interesting settling
point that doesn't, well, seem obvious.  OR that the gate then tries
to shift states before it's supposed to and then we see a beat
frequency between the internals and the noise or something else goofy.
Click to expand...
If the loop gain is high it will want to oscillate and noise will push
it into oscillation. If the loop gain is <1 noise will be amplified
but it will stabilize back to the midpoint.

Though I'm sure it's nothing more than the settling like you suggest
{shrug}.  I just find it intriguing.
Click to expand...
It *is* an amplifier, just not a very good one.
 
On May 22, 1:21 pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Fri, 22 May 2009 07:12:03 -0700 (PDT), "Thomas G. Marshall"



tgmfo...@gmail.com> wrote:

I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.

Now I guessing that it's not going to look anything like a clean
square wave, because the transition voltages would be met mighty
fast.  But are the transitions monotonic?  If not, does any noise goof
up which direction its transitioning when switching that fast?

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state?  At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.

Thanks!

Old slow 74-type TTL had essentially one low-gain stage, 1st order
response, so a simple gate would usually stabilize at about +1.2 volts
DC. Later gen faster parts, like AS and F will probably oscillate.
HC-type CMOS parts have multiple internal stages, higher-order delay,
so usually oscillate. Early ECL (10K, 10KH) would DC stabilize too;
faster, higher gain parts (Eclips, EL, EP) will oscillate.

10K type ECL was often used as a fast amplifier. A 7400 gate can be
used as an amplifier, too.

John
Click to expand...
Great responses you two! Thanks!
 
On 2009-05-22, Thomas G. Marshall <tgmforum@gmail.com> wrote:
I no longer have access to a scope; I've been wondering about this off
and on.

Back in college I pondered a NAND gate with one input held high, and
the other input being tied to the output.

Basically wondering about the oscilation, and just how "clean" it
might be.
Click to expand...
with a direct connection it might not even oscillate.
put a twin-tee or other phase inversion network there and it's likely
to though.

I suppose what I'm asking is: Is there an odd place where the
transition voltages from true to false (and back) are not "quite"
enough there to have the NAND output enter an completely undefined
state? At first I was assuming that the there would just be a tight
cycling around the transition but I'm not sure now what noise and any
need for the analog circuits to be "left alone" might cause.
Click to expand...
by adding negative feedback people have used biased gates as low power
audio amplifiers in the past.
 
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