ofdm implemtation help needed

[Just an Illusion]

Hi

Ralf Hildebrandt a écrit :

tvptcm@gmail.com schrieb:
snip
2) Is it better to write in Verilog or not and why?

If your boss did not make a decision for you: Use the HDL you are
familiar with!
No lot more recommendation except than I the design must be use by an

external 'customer' team, it is better if you check with them which HDL
language & tools they use to verify if they are valid for you too.

For example, if you project have US team, they certainly use more
Verilog than VHDL. But European countries have more VHDL than Verilog
design. I am not sure for Indian or Chinese.

I prefer VHDL, because it is strongly typed. This means small typing
errors will be detected as errors and are unlikely valid expressions
with different meaning.

Have a look at the book "HDL Chip Design" by Douglas J. Smith. It
teaches both languages at the same time.
That is a very good recommendation.

I prefer the VHDL too, but I think than you can remember you these
languages history to help your choice :
- VHDL is a derivation of software point of view (ADA) to the netlist
point of view
- Verilog is a rationalisation of the netlist like a software approach

The both approach netlist (more physical) and software (more
logical/mathematical) are both valid, but some time the requirement of
one side are ignored by the other side : in ex. memory allocation is
infinite in software, but limited in hardware.

One of my favourite Verilog feature is the capacity to easily define the
initial state of the system. The way use by Verilg is more synthesizer
driven, than VHDL one.
But VHDL is more easy to interface with other software language because
they share common approach of variables.

In summary : if you want define your own 'non standard' design
environment with non classical EDA software tools, better choice is
certainly the VHDL. If you want use analog designer team, better choice
is certainly the Verilog. In both case you made digital design, then the
designer must masterized the boolean logic way, with perhaps a basic
knowledge on synchronous and asynchronous systems.

Ralf

JaI

 

I am going to implement VHDL code of ofdm transceiver, later I will
synthesize the code using Nanoboard 1 & Altium designer. Though I have
few doubts that is needed to be answered:
1) Which Fpga is better out of those to synthsize into: Xilins Spartan
or Altera Cyclone?
2) Is it better to write in Verilog or not and why?

P.S. That is a small project so budget is tight and is only for
development & testing purposes. Thanks for any kind of help.

 

[Ralf Hildebrandt]

tvptcm@gmail.com schrieb:

1) Which Fpga is better out of those to synthsize into: Xilins Spartan
or Altera Cyclone?

Do you need any special block inside the FPGA? (BlockRAM (How much?),
MAC units, many multipliers, a CPU core, many clock buffers)

If you have thought about what you need and how big everything will
become, then you can chose the right FPGA.

If you are familiar with one FPGA vendor it is often easier to stay with
this one. If you already have the tools, it is cheaper if you continue
to use them. If you have colleagues in other parts of your company that
already use FPGAs by one vendor it is nice to go to them and ask them if
you have a problem, if you are using the same tools.

The FPGA tools should offer you synthesis to any type of FPGA from the
appropriate vendor. So you can easily chose a FPGA that is big enough.


For my opinion choosing the FPGA is a step that comes very late during
the design process. Often I spend months building my component and then
twice the time to test it in my simulation environment. And finally I
move to the desired target (ASIC, FPGA).


Let me give you an example: At the moment I do a design which has seen
two FPGAs: Altera Flex10k (so old that you could call it a dinosaur) and
Xilinx Virtex 5. My component only needs a "see of gates" and some
small amount of block RAM. It has a lot of clock gating (and the Flex10k
has only one clock buffer). The decision for Xilinx was because enough
Xilinx Software licenses are available in my company.

2) Is it better to write in Verilog or not and why?

If your boss did not make a decision for you: Use the HDL you are
familiar with!

I prefer VHDL, because it is strongly typed. This means small typing
errors will be detected as errors and are unlikely valid expressions
with different meaning.

Have a look at the book "HDL Chip Design" by Douglas J. Smith. It
teaches both languages at the same time.


Ralf

 

On Jan 10, 4:47 pm, Just an Illusion <illusion_to_...@yahoo.fr> wrote:

Hi

Ralf Hildebrandt a écrit :> tvp...@gmail.com schrieb:
snip
2) Is it better to write in Verilog or not and why?

If your boss did not make a decision for you: Use the HDL you are
familiar with!

No lot more recommendation except than I the design must be use by an
external 'customer' team, it is better if you check with them which HDL
language & tools they use to verify if they are valid for you too.

For example, if you project have US team, they certainly use more
Verilog than VHDL. But European countries have more VHDL than Verilog
design. I am not sure for Indian or Chinese.

I prefer VHDL, because it is strongly typed. This means small typing
errors will be detected as errors and are unlikely valid expressions
with different meaning.

Have a look at the book "HDL Chip Design" by Douglas J. Smith. It
teaches both languages at the same time.

That is a very good recommendation.

I prefer the VHDL too, but I think than you can remember you these
languages history to help your choice :
- VHDL is a derivation of software point of view (ADA) to the netlist
point of view
- Verilog is a rationalisation of the netlist like a software approach

The both approach netlist (more physical) and software (more
logical/mathematical) are both valid, but some time the requirement of
one side are ignored by the other side : in ex. memory allocation is
infinite in software, but limited in hardware.

One of my favourite Verilog feature is the capacity to easily define the
initial state of the system. The way use by Verilg is more synthesizer
driven, than VHDL one.
But VHDL is more easy to interface with other software language because
they share common approach of variables.

In summary : if you want define your own 'non standard' design
environment with non classical EDA software tools, better choice is
certainly the VHDL. If you want use analog designer team, better choice
is certainly the Verilog. In both case you made digital design, then the
designer must masterized the boolean logic way, with perhaps a basic
knowledge on synchronous and asynchronous systems.



Ralf

JaI

Hi,
I'm Ghassan an Electronic/Telecomm. Eng. currently studying M.Sc.
My project is to build an OFDM Transceiver on FPGA.
I think we can commuinicate with each other about this topic if you
don't
mind ?

my e-mail is : g.almamar@gmail.com