Odd Oversampling

[ALuPin]

Hi newsgroup,

maybe someone of you out there has faced some similar problem:

I want to sample 16MHz data with a 125MHz clock.

But 125/16 = 7.8125

Is there some tricky method to perform this kind of oversampling ?

The only thing I know is the Bresenham algorithm, but could that
be the solution ?

Thank you in advance.

Rgds

 

[ALuPin]

"Symon" <symon_brewer@hotmail.com> wrote in message news:<4263e34f@x-privat.org>...

"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message
news:ft8761tdcb22fop7o910lkc8l5qlirhueg@4ax.com...
If you don't have access to the original 16MHz clock, you can
either try to recover it by locking a digital PLL on to the
data transitions (7x oversampling is *just* about enough
to be able to do this easily)

It's easy enough with just 4 times oversampling. XAPP224 shows how to do it
at 400Mb+ data rates.
Cheers, Syms.
Please correct me if I got the problem wrong.

Is it right that I could define a counter (clocked with 125MHz)
and define one counter position as the sample point which is located
in the middle position neighborhood of the bit to sample ?
The counter would be quasi started if the first transition is
recognized. This transition could be recognized with a two stage flip
flop chain in the 125Mhz
clock domain.
The problem would be that the following sample points would walk
because
125/16 is a fraction number. Is that right ?

Could that sample point walk even then if the oversample factor 125/x
would
be an integer number for example 120MHz/12MHz when 120MHz having 0.05%
tolerance
and 20MHz having 0.02% tolerance ?


If I have 7 times oversampling would I need then an input stage
with seven stages (XAPP224)? What additional clocks would I need then
?
Or are four clocks sufficient?

Thank you in advance.

Rgds
André

 

[ALuPin]

One more question:

The quasi "oversample" solution in XAPP224 does imply that the sample
clock is the same as the clock from the incoming data stream.

But in my situation I have a clock that is 7-8 times faster.

Please clarify ...

Thank you.

Rgds
André

 

[Peter Alfke]

Here is a circuit that generates 16 MHz from a 125 MHz clock:
Use a Xilinx DCM with simultaneous multiply by 16 and division by 25.
That gives you 80 MHz, which might be convenient for 5x oversampling.
Peter Alfke, Xilinx Applications

 

[ALuPin]

The 16MHz stands for an external data stream. I have no direct clock
recovery of that data stream. The 125MHz comes from a PLL. The input
clock of the PLL
is not the source clock of the data stream.

I will think about your suggestions.

Thank you to all.

Rgds
André