Odd error in code

[rickman]

This one has me stumped. I am thinking that the actual error must be
somewhere other than where the tool is pointing, but I can't figure it
out.

The error is "(201, 28): Operator "=" is not defined for such
operands" and points to the first use of DemPhase in the first line.

CarZCross <= '1' when (((DemPhase = 7) or (DemPhase = 8)) and
(CDCDataRcv'high = '1'))
'1' when (DemPhase = 9) else
'0';

DemPhase is declared...

signal DemPhase : natural range 1 to 9 := 9;


I am also seeing an error on assignments from one element of a signed
(std_numeric) signal to a std_logic signal. "Assignment target
incompatible with right side. Expected type "std_ulogic". I thought
these were acceptable types to mix. Plus, I thought this was working
fine until I made some other changes.

CDCDataSign <= CDCDataRcv'high;

Any suggestions? The libraries should be ok since this design has
been working for months.

 

[Mike Treseler]

rickman wrote:

The error is "(201, 28): Operator "=" is not defined for such
operands" and points to the first use of DemPhase in the first line.

CarZCross <= '1' when (((DemPhase = 7) or (DemPhase = 8))
and (CDCDataRcv'high = '1'))
'1' when (DemPhase = 9) else
'0';
DemPhase is declared...
signal DemPhase : natural range 1 to 9 := 9;

Looks OK to me if that is the type.
Post post a complete unit that compiles (or ought to)
and I'll have a look.

I am also seeing an error on assignments from one element of a signed
(std_numeric) signal to a std_logic signal. "Assignment target
incompatible with right side. Expected type "std_ulogic". I thought
these were acceptable types to mix.

Should be. Are you using that brand X simulator again?

-- Mike Treseler

 

[Tricky]

                CDCDataSign             <= CDCDataRcv'high;

try:
CDCDataSign <= CDCDataRcv(CDCDataRcv'high);

instead. the 'high attribute is just a integer.

 

[rickman]

On Aug 5, 10:19 am, Mike Treseler <mtreseler@gmail.com> wrote:

rickman wrote:
The error is "(201, 28): Operator "=" is not defined for such
operands" and points to the first use of DemPhase in the first line.

CarZCross <= '1' when (((DemPhase = 7) or (DemPhase = 8))
and (CDCDataRcv'high = '1'))
'1' when (DemPhase = 9) else
'0';
DemPhase is declared...
signal DemPhase : natural range 1 to 9 := 9;

Looks OK to me if that is the type.
Post post a complete unit that compiles (or ought to)
and I'll have a look.

I am also seeing an error on assignments from one element of a signed
(std_numeric) signal to a std_logic signal. "Assignment target
incompatible with right side. Expected type "std_ulogic". I thought
these were acceptable types to mix.

Should be. Are you using that brand X simulator again?

Mike, thanks. No, I am using Active HDL. It has been pretty nice so
far and will catch bugs that the synthesis tool doesn't (and vice
versa). The fact that code that was working just fine (and is clearly
correct) has now broken says to me that the real problem is elsewhere,
but how to find it?

The source is a bit large to post here and has two library files.
I've zipped them up and email it. I forgot to change the file
extension, so it may go into your quarantine folder.

Rick

 

[rickman]

On Aug 5, 10:29 am, Tricky <Trickyh...@gmail.com> wrote:

CDCDataSign <= CDCDataRcv'high;

try:
CDCDataSign <= CDCDataRcv(CDCDataRcv'high);

instead. the 'high attribute is just a integer.

Yeah, I just figured it out. I guess my unrelated changes made more
of a change than I thought. Odd that it seemed to flag DemPhase. I
guess it just puts the flag at the start of the WHEN expression rather
than flag the actual signal giving the error.

Thanks,

Rick

 

[Mike Treseler]

rickman wrote:

Yeah, I just figured it out. I guess my unrelated changes made more
of a change than I thought. Odd that it seemed to flag DemPhase. I
guess it just puts the flag at the start of the WHEN expression rather
than flag the actual signal giving the error.

Modelsim gets it right:

cd /evtfs/home/tres/vhdl/carrier/
vcom -2002 -quiet -work work Carrier.vhd
** Error: Carrier.vhd(203): No feasible entries for infix operator "=".
** Error: Carrier.vhd(203): Bad expression in right operand of infix
expression "and".
** Error: Carrier.vhd(203): Type error resolving infix expression "and"
as type std.standard.boolean.

Here's the fix:
--= (CDCDataRcv'high = '1')) else
(CDCDataRcv(CDCDataRcv'high) = '1')) else

** Error: Carrier.vhd(236): Attribute "high" returns type
std.standard.natural; expecting type ieee.std_logic_1164.std_logic.
** Error: Carrier.vhd(245): No feasible entries for subprogram "posedge".
** Error: Carrier.vhd(245): Type error resolving infix expression "xor"
as type std.standard.boolean.

Here's the fixes:

--= CDCDataSign <= CDCDataRcv'high;
CDCDataSign <= CDCDataRcv(CDCDataRcv'high);

--= if (PosEdge(CDCDataRcv'high, CDCDataSign) xor CarSync) then
if (PosEdge(CDCDataRcv(CDCDataRcv'high), CDCDataSign) xor CarSync)
then

Thanks,

You're welcome.
Nice use of functions.
Might want to add this in architecture scope:

impure function msb_high
return std_ulogic is
begin
return CDCDataRcv(CDCDataRcv'high);
end function msb_high;

impure function msb_high
return boolean is
begin
return msb_high = '1';
end function msb_high;


then you can hide the details like this:

CDCDataSign <= msb_high;
...
if msb_high then ... etc.

-- Mike Treseler