numeric_std and signed "/" operator

[Valentino]

Hi,

I'm developing a digital signal processing algorithm on Xilinx Virtex2
FPGA. I use the Xilinx ISE 6.1i developing environment.
I'm trying to use the "/" (divisor) operator included in the ieee
"numeric_std" library but the systesis produces the following error
message:

"ERROR:Xst:769 - C:/test/div.vhd line 35: Operator <INVALID OPERATOR>
must have constant operands or first operand must be power of 2"

Does the ieee "/" operator is really defined for constant or power of
2 operators only?

How can I evaluate Q=NUM/DEN, where NUM and DEN are not constant, not
of power 2 and of type SIGNED ?

I already tested the Xilinx "Pipelined Divider V2.0" core but I can't
use it because of it's very high latency.

Thanks.

------------------------------

It follows the source code that generates the error message:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;


entity div is Port (
clk: in std_logic;
NUM: in SIGNED(15 downto 0);
DEN: in SIGNED(15 downto 0);
Q: out SIGNED(15 downto 0) );
end div;


architecture Behavioral of div is
begin

process (clk, NUM, DEN)
begin
if clk='1' and clk'event then
Q <= NUM/DEN;
end if;
end process;

end Behavioral;

 

[Simon Peacock]

I believe its not an integer divide routine but a binary one.. if it was..
they would have the same latency as the Xilinx pipelined version.

divide by 2 is of course, easy because that's native to binary.

Simon

"Valentino" <vlentn@yahoo.it> wrote in message
news:79780d60.0312101004.8a90d74@posting.google.com...

Hi,

I'm developing a digital signal processing algorithm on Xilinx Virtex2
FPGA. I use the Xilinx ISE 6.1i developing environment.
I'm trying to use the "/" (divisor) operator included in the ieee
"numeric_std" library but the systesis produces the following error
message:

"ERROR:Xst:769 - C:/test/div.vhd line 35: Operator <INVALID OPERATOR
must have constant operands or first operand must be power of 2"

Does the ieee "/" operator is really defined for constant or power of
2 operators only?

How can I evaluate Q=NUM/DEN, where NUM and DEN are not constant, not
of power 2 and of type SIGNED ?

I already tested the Xilinx "Pipelined Divider V2.0" core but I can't
use it because of it's very high latency.

Thanks.

------------------------------

It follows the source code that generates the error message:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;


entity div is Port (
clk: in std_logic;
NUM: in SIGNED(15 downto 0);
DEN: in SIGNED(15 downto 0);
Q: out SIGNED(15 downto 0) );
end div;


architecture Behavioral of div is
begin

process (clk, NUM, DEN)
begin
if clk='1' and clk'event then
Q <= NUM/DEN;
end if;
end process;

end Behavioral;