Number of Logic Elements Estimate

[nfirtaps]

Could someone give me a best estimate for the number of LE's the
following design will need:

8 Channel signal processing core.
Each channel has the following
- Comb Filter
- 4 FIR filters with around 11 taps
- 4 Decimating filters also with around 11 taps
- 2 128 tap customizable Taps

The design also needs 2 512x16 bit FIFO's

Would someone imaging this could be done in 8K LE's or is something
like 30K a better estimate?

Thanks

 

[Mike Treseler]

nfirtaps wrote:

Could someone give me a best estimate for the number of LE's the
following design will need:

8 Channel signal processing core.
Each channel has the following
- Comb Filter
- 4 FIR filters with around 11 taps
- 4 Decimating filters also with around 11 taps
- 2 128 tap customizable Taps

I would code up an example and run ise or quartus.

-- Mike Treseler

 

[nfirtaps]

I would code up an example and run ise or quartus.
Could someone please respond with a best estimate, I am fully aware I

could code up an example.



Mike Treseler wrote:

nfirtaps wrote:
Could someone give me a best estimate for the number of LE's the
following design will need:

8 Channel signal processing core.
Each channel has the following
- Comb Filter
- 4 FIR filters with around 11 taps
- 4 Decimating filters also with around 11 taps
- 2 128 tap customizable Taps

I would code up an example and run ise or quartus.

-- Mike Treseler

 

[Jonathan Bromley]

On 10 Aug 2006 10:28:04 -0700, "nfirtaps" <lloyd.rochester@gmail.com>
wrote:

I would code up an example and run ise or quartus.
Could someone please respond with a best estimate, I am fully aware I
could code up an example.

urrrrm, if I were about to start a project like that I would urgently
want to understand how to work that sort of thing out for myself,
and the best way to understand is by doing it - unless you're willing
to pay for the work...

8 Channel signal processing core.

So, is it running so fast that you must create eight separate
channel instances? Or slowly enough that you can time-share one
channel instance among the eight channels, with some additional
storage?

Each channel has the following
- Comb Filter

Frequency spacing? Precision? Speed?

- 4 FIR filters with around 11 taps

Coefficient width? Data width? Speed? Can you timeshare
the multiply-accumulate hardware, or do you need 11 MACs
for the 11 taps? Is the data and coefficient width within the
size limit of your FPGA's dedicated multipliers, and are there
enough of them on your chosen FPGA? 8x4x11 MACs
sounds like a lot of hardware to me... Can you do bit-serial?

- 4 Decimating filters also with around 11 taps

Width and speed again...

- 2 128 tap customizable Taps

What is a customizable Tap? (No plumbing jokes, please)

If the sample rate is sufficiently low I could do the whole thing
with a programmable CPU - Microblaze, Nios or whatever - and
a bunch of memory. The LE counts for such things are well
publicized. I'm guessing, though, that's not what you intend.

So far, Mike's suggestion sounds best to me. Please don't get
impatient with us until you've put in some effort yourself!
As I hope I've shown, it is completely impossible to make
a realistic size estimate from the information you've given.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[nfirtaps]

Rather, than waste everyones time, I am going to take Mike's advice and
implement this DDC in IDE, I have to do the implementation anyways.
Thanks.


Jonathan Bromley wrote:

On 10 Aug 2006 10:28:04 -0700, "nfirtaps" <lloyd.rochester@gmail.com
wrote:

I would code up an example and run ise or quartus.
Could someone please respond with a best estimate, I am fully aware I
could code up an example.

urrrrm, if I were about to start a project like that I would urgently
want to understand how to work that sort of thing out for myself,
and the best way to understand is by doing it - unless you're willing
to pay for the work...

8 Channel signal processing core.

So, is it running so fast that you must create eight separate
channel instances? Or slowly enough that you can time-share one
channel instance among the eight channels, with some additional
storage?

Each channel has the following
- Comb Filter

Frequency spacing? Precision? Speed?

- 4 FIR filters with around 11 taps

Coefficient width? Data width? Speed? Can you timeshare
the multiply-accumulate hardware, or do you need 11 MACs
for the 11 taps? Is the data and coefficient width within the
size limit of your FPGA's dedicated multipliers, and are there
enough of them on your chosen FPGA? 8x4x11 MACs
sounds like a lot of hardware to me... Can you do bit-serial?

- 4 Decimating filters also with around 11 taps

Width and speed again...

- 2 128 tap customizable Taps

What is a customizable Tap? (No plumbing jokes, please)

If the sample rate is sufficiently low I could do the whole thing
with a programmable CPU - Microblaze, Nios or whatever - and
a bunch of memory. The LE counts for such things are well
publicized. I'm guessing, though, that's not what you intend.

So far, Mike's suggestion sounds best to me. Please don't get
impatient with us until you've put in some effort yourself!
As I hope I've shown, it is completely impossible to make
a realistic size estimate from the information you've given.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.