null statements...

[Jluis]

Hi everyone?
I have some problem with buffer definition.
I coded a program and I want to transfer outbuf4 <= inbuf4 when Ira=1
and when Ira=0 I want that outbuf <= (null or open or disconected,but
not high impedance). I know that I can use outbuf <= "ZZZ". But my
question is... are there some way to do that without use HIGH
IMPEDANCE? i TRIED TO PUT NULL AND OPEN SENTENCES, BUT MAXPLUS GET A
ERROR MESSAGES. i NEED TO SYNTHETIZED.
MY DESIGN REQUIREMENTS IS TO LEFT TOTALLY OPEN WHEN Ira =0.

ANY IDEAS.........
tHANKS IN ADVANCE
JLUIS
MEXICO


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY buff4_ir IS
PORT( Ira: IN std_logic;
inbuf4: IN std_logic_vector(2 DOWNTO 0);
outbuf4: OUT std_logic_vector(2 DOWNTO 0));
END buff4_ir;

ARCHITECTURE archbuff4_ir OF buff4_ir IS
BEGIN
PROCESS(Ira, inbuf4)
BEGIN
IF Ira = '1' then
outbuf4 <= inbuf4;
ELSE
outbuf4 <= null;
end if;
end process;
END archbuff4_ir;

 

[Tim Hubberstey]

Jluis wrote:

Hi everyone?
I have some problem with buffer definition.
I coded a program and I want to transfer outbuf4 <= inbuf4 when Ira=1
and when Ira=0 I want that outbuf <= (null or open or disconected,but
not high impedance). I know that I can use outbuf <= "ZZZ". But my
question is... are there some way to do that without use HIGH
IMPEDANCE?

No. Think hardware: null or open or disconected _IS_ high Z.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

 

[Charles Bailey]

"Jluis" <joself@cimat.mx> wrote in message
news:26e0122e.0405241936.3af04341@posting.google.com...

Hi everyone?
I have some problem with buffer definition.
I coded a program and I want to transfer outbuf4 <= inbuf4 when Ira=1
and when Ira=0 I want that outbuf <= (null or open or disconected,but
not high impedance). I know that I can use outbuf <= "ZZZ". But my
question is... are there some way to do that without use HIGH
IMPEDANCE? i TRIED TO PUT NULL AND OPEN SENTENCES, BUT MAXPLUS GET A
ERROR MESSAGES. i NEED TO SYNTHETIZED.
MY DESIGN REQUIREMENTS IS TO LEFT TOTALLY OPEN WHEN Ira =0.
This requirement doesn't make sense. What is wrong with setting the

output to Z, high impedance?

ANY IDEAS.........
tHANKS IN ADVANCE
JLUIS
MEXICO


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

ENTITY buff4_ir IS
PORT( Ira: IN std_logic;
inbuf4: IN std_logic_vector(2 DOWNTO 0);
outbuf4: OUT std_logic_vector(2 DOWNTO 0));
END buff4_ir;

ARCHITECTURE archbuff4_ir OF buff4_ir IS
BEGIN
PROCESS(Ira, inbuf4)
BEGIN
IF Ira = '1' then
outbuf4 <= inbuf4;
ELSE
outbuf4 <= null;
"null;" is a statement, not a value. Can't do this.

end if;
end process;
END archbuff4_ir;