"NOT" in PORT MAP

[ALuPin@web.de]

Hi,

when I try to integrate NOT in PORT MAP
under Modelsim I get a error message:

i_test : test
PORT MAP ( ls_test => NOT ls_test2,
...
);

whereas the following construct is permitted
by Modelsim:

i_test : test
PORT MAP ( ls_test => "NOT" (ls_test2),
...
);

When synthesizing the design (Synplify) the first
construct is OK.
Will the second one also be accepted ?

Thank you for your opinion.

Rgds
André

 

[Jonathan Bromley]

On 13 Jul 2006 01:21:49 -0700, "ALuPin@web.de" <ALuPin@web.de> wrote:

when I try to integrate NOT in PORT MAP
under Modelsim I get a error message:

i_test : test
PORT MAP ( ls_test => NOT ls_test2,
...
);

whereas the following construct is permitted
by Modelsim:

i_test : test
PORT MAP ( ls_test => "NOT" (ls_test2),
...
);

When synthesizing the design (Synplify) the first
construct is OK.
Will the second one also be accepted ?

The second example is legal VHDL - you can use any
monadic function in a port map. I don't know whether
Synplify is OK with it, but it *should* be. It's more
common to use this feature to achieve type conversion
across a port map, but the rules say that any function
is OK.

The first example puts an expression in the port map.
This is illegal, but Synplify is apparently tolerating it -
note that this is easy for a synthesis tool, because the
Verilog equivalent *is* legal.

VHDL-200x is doing something about expressions in
port maps, but it's quite tricky and I'm not sure what
progress they have made.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[ALuPin@web.de]

Hi Jonathan,

thank you for your info.

Rgds
André

 

[Andy]

The first example is an expression that calls a function, but it is not
a function call, and therefore is not legal vhdl. The second example is
the way to call an operator as a function, and is legal vhdl (port
conversion function). Conversion functions need not actually change
the type of the argument. I wrote a vhdl netlister once for Valid
simulation schematics that used this feature to handle bubbled pins on
simulation primitives.

Port conversion functions are not included in the standard
synthesizable vhdl subset, but Synplicity has a long history of
recognizing more than the standard subset. Just know that it may not
work with other synthesis tools.

I saw a paper at an hdlcon years ago where they used port conversion
functions in configurations to great effect. It allowed them to
seamlessly swap in and out different models, with different port data
types, in the same testbench, without having to write wrapper code.

Note that the conversion function will result in a delta delay across
the port.

Andy


ALuPin@web.de wrote:

Hi Jonathan,

thank you for your info.

Rgds
André