not able to write to addr loc x0

[fpgawizz]

I am using the following code to write some contents to an external memory.
a data_ready signal is sent to my mem controller to do the write.the
problem i have here is that i want my data to go into addr 0 through
5..instead i find its there in address 1 through 6..i am not sure where i
am introducing this offset..i do have a counter that counts up to each mem
location..
i am pasting my code here..am i doing the counting the wrong way? thanks
("N" is my address counter)


Receive_Process: Process(clk_6_51u,Din)
variable temp : std_logic;
begin
if clk_6_51u'event and clk_6_51u = '1' then

case statevar is
when rst =>
data_ready_w <= '0';
data_ready_r <= '0';
data <= X"00";
LD <= "00000000";
N <= "00000000";
statevar <= idle;

when idle =>
shift_reg <= X"FFFF";
cnt <= 0;
statevar <= startbit;
when startbit =>
shift_reg <= Din & shift_reg(15 downto 1);
if shift_reg = X"0FFF" then
statevar <= d0;
else
statevar <= startbit;
end if;

when d0 =>
cnt <= cnt + 1;
if cnt < (16) then
statevar <= d0;
else
data(0) <= Din;
statevar <= d1;
end if;
when d1 =>
cnt <= cnt + 1;
if cnt < (32) then
statevar <= d1;
else
data(1) <= Din;
statevar <= d2;
end if;
when d2 =>
cnt <= cnt + 1;
if cnt < (48) then
statevar <= d2;
else
data(2) <= Din;
statevar <= d3;
end if;
when d3 =>
cnt <= cnt + 1;
if cnt < (64) then
statevar <= d3;
else data(3) <= Din; statevar <= d4;
end if;
when d4 =>
cnt <= cnt + 1;
if cnt < (80) then
statevar <= d4;
else
data(4) <= Din;
statevar <= d5;
end if;
when d5 =>
cnt <= cnt + 1;
if cnt < (96) then
statevar <= d5;
else
data(5) <= Din;
statevar <= d6;
end if;
when d6 =>
cnt <= cnt + 1;
if cnt < (112) then
statevar <= d6;
else
data(6) <= Din;
statevar <= d7;
end if;
when d7 =>
cnt <= cnt + 1;
if cnt < (128) then
statevar <= d7;
else
data(7) <= Din;
LD <= data;
statevar <= stopbit;
end if;
when stopbit =>
cnt <= cnt + 1;
if cnt < (144) then
statevar <= stopbit;
else
temp := Din;
Statevar <= dataready;
end if;
when dataready =>
data_ready_w <= '1';
statevar <= incN;
when incN =>
data_ready_w <= '0';
N <= N + 1;
statevar <= idle;
end case;
end if;

end process Receive_Process;