L
luvy
Guest
hi,
i am making a project on synchronous FIFO block using verilog HDL. i
have made a top level module which includes read control logic, write
control logic, memory array(includes just inputs and outputs). now to
read the 16 bit input values i have made a module for read control
logic so Can u plz tell me the logic to generate almost empty flag and
also for read pointer and read valid data generation. i have taken
depth =16, addr_width=4, data width=16, almost empty=3, write address
width=4, read address width=4, read ptr width=5, write ptr width=5.
your help will surely be useful for me to understand it. reply asap.
thank you
i am making a project on synchronous FIFO block using verilog HDL. i
have made a top level module which includes read control logic, write
control logic, memory array(includes just inputs and outputs). now to
read the 16 bit input values i have made a module for read control
logic so Can u plz tell me the logic to generate almost empty flag and
also for read pointer and read valid data generation. i have taken
depth =16, addr_width=4, data width=16, almost empty=3, write address
width=4, read address width=4, read ptr width=5, write ptr width=5.
your help will surely be useful for me to understand it. reply asap.
thank you