non-static others choice

N

Nicolas Matringe

Guest
Hi
I have a warning and I wonder if I should worry about it or not (I think
it's safe but maybe there's a hidden trap there):

....
generic (length : natural := 4);
....
signal slvec : std_logic_vector(length - 1 downto 0)
....
process (clk, rst)
begin
if rst = '1' then
slvec <= (0 => '1', others => '0');
elsif rising_edge(clk) then
....

ModelSim issues a warning:
"Non-static aggregate with multiple choices has non-static others choice."

Any advice?

Thanks in advance
Nicolas
 
Nicolas Matringe <nmatringe@reflex-consulting.com> wrote in message news:<3FD83C6E.1080603@reflex-consulting.com>...
Hi
I have a warning and I wonder if I should worry about it or not (I think
it's safe but maybe there's a hidden trap there):

...
generic (length : natural := 4);
...
signal slvec : std_logic_vector(length - 1 downto 0)
...
process (clk, rst)
begin
if rst = '1' then
slvec <= (0 => '1', others => '0');
elsif rising_edge(clk) then
...

ModelSim issues a warning:
"Non-static aggregate with multiple choices has non-static others choice."

Any advice?

Thanks in advance
Nicolas
Since the range of the signal "slvec" is globally static (should be
locally static), this assignment is illegal as per VHDL LRM. Same
rules are cases switches and "when" assignments. However, some(most ?)
simulators allow this with a warning which you are seeing. It should
be fine.

I feel this restriction in VHDL is unnecessary and a simplification
made to make elaboration easier. Lord knows it is complicated enough
already.

Good Luck
Debjyoti
 
Nicolas Matringe wrote:
Hi
I have a warning and I wonder if I should worry about it or not (I think
it's safe but maybe there's a hidden trap there):

...
generic (length : natural := 4);
...
signal slvec : std_logic_vector(length - 1 downto 0)
...
process (clk, rst)
begin
if rst = '1' then
slvec <= (0 => '1', others => '0');
elsif rising_edge(clk) then
...

ModelSim issues a warning:
"Non-static aggregate with multiple choices has non-static others choice."

Any advice?
Use:

if rst = '1' then
slvec(slvec'range => '0');
slvec(0 <= '1');
elsif rising_edge(clk) then

Paul.
 

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