non power of 2 mux/decoder

[romi]

Consider the parameterized decoder and mux below. With the N
parameter set to 3, the decoder can potentially be "overshifted" and
the selector to the mux can select a non-existent input. In
simulation, the decoder will put out a 0 when it is overshifted. The
mux will output an 'x' when the selector is too large. A synthesis
tool probably has to honor the 0 output when the decoder is
overshifted and synthesize appropriately. However, since the mux can
output an 'x', a synthesis tool can probably optimize the 'x' case as
a don't care. Will equivalence checkers then complain since we are
simulating an 'x' and synthesizing to something that is not 'x'?
Thanks!

module test
#(
parameter
N=3,
W=2
)
(
input [W-1:0] shift,
input [W-1:0] sel,

output mux
);

// Decoder
wire [N-1:0] dcd=(1'b1 << shift);


// Mux
wire mux = dcd[sel];

endmodule