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Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
how fast is really fast?
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
how fast is really fast?
60 to maybe 150 MHz.
The faster it is, the fewer bits I\'d need. I guess I could overkill
with a really fast ADC, 250 MHz maybe, and live with the pipeline
delay and price. The really fast DACs are pipelined nowadays too.
I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that
was made from parts, namely 63 comparators and a bunch of ECL. It
didn\'t last long, as integrated ADCs got good soon after.
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
On 8/25/2020 2:34 PM, John Larkin wrote:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
Low value resistors, fast NAND gates:
http://zpostbox.ru/simple_adc.html
tirsdag den 25. august 2020 kl. 21.29.41 UTC+2 skrev John Larkin:
On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
how fast is really fast?
60 to maybe 150 MHz.
The faster it is, the fewer bits I\'d need. I guess I could overkill
with a really fast ADC, 250 MHz maybe, and live with the pipeline
delay and price. The really fast DACs are pipelined nowadays too.
I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that
was made from parts, namely 63 comparators and a bunch of ECL. It
didn\'t last long, as integrated ADCs got good soon after.
how terrible would a string of resistors and a bunch of LVDS recievers
on an FPGA be?
a couple volt divided by 16/32 is right around 100mV minimum diff voltage
for an LVDS receiver
On Tue, 25 Aug 2020 13:12:50 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
tirsdag den 25. august 2020 kl. 21.29.41 UTC+2 skrev John Larkin:
On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
how fast is really fast?
60 to maybe 150 MHz.
The faster it is, the fewer bits I\'d need. I guess I could overkill
with a really fast ADC, 250 MHz maybe, and live with the pipeline
delay and price. The really fast DACs are pipelined nowadays too.
I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that
was made from parts, namely 63 comparators and a bunch of ECL. It
didn\'t last long, as integrated ADCs got good soon after.
how terrible would a string of resistors and a bunch of LVDS recievers
on an FPGA be?
a couple volt divided by 16/32 is right around 100mV minimum diff voltage
for an LVDS receiver
Interesting idea. If we use a ZYNQ, we\'ll have a zillion pins to
spare. A 4-bit, 250 MHz flash ADC wouldn\'t be unreasonable.
tirsdag den 25. august 2020 kl. 22.47.42 UTC+2 skrev John Larkin:
On Tue, 25 Aug 2020 13:12:50 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
tirsdag den 25. august 2020 kl. 21.29.41 UTC+2 skrev John Larkin:
On Tue, 25 Aug 2020 12:12:32 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:
tirsdag den 25. august 2020 kl. 20.34.31 UTC+2 skrev John Larkin:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
how fast is really fast?
60 to maybe 150 MHz.
The faster it is, the fewer bits I\'d need. I guess I could overkill
with a really fast ADC, 250 MHz maybe, and live with the pipeline
delay and price. The really fast DACs are pipelined nowadays too.
I once worked for an outfit that sold a CAMAC 6-bit, 50 MHz ADC that
was made from parts, namely 63 comparators and a bunch of ECL. It
didn\'t last long, as integrated ADCs got good soon after.
how terrible would a string of resistors and a bunch of LVDS recievers
on an FPGA be?
a couple volt divided by 16/32 is right around 100mV minimum diff voltage
for an LVDS receiver
Interesting idea. If we use a ZYNQ, we\'ll have a zillion pins to
spare. A 4-bit, 250 MHz flash ADC wouldn\'t be unreasonable.
driving it might be interesting, I think each pad is ~8pf
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
What are you trying to do that can\'t wait a few clock cycles?
-- john, KE5FX
On 2020-08-25 14:34, John Larkin wrote:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
Plus they had fixed-pattern jitter due to the different RC delays on the
resistor string.
How fast is fast?
Cheers
Phil Hobbs
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), \"John Miles, KE5FX\"
jmiles@gmail.com> wrote:
On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
....
It\'s a PLL, and lag slows down the loop dynamics.
I start an LC oscillator when I get a trigger, and use it to time out
delays. The ADC is clocked from an OCXO and observes the waveform of
the triggered LC oscillator, and I close a loop to lock the LC to the
XO. Actually, the LC frequency is whatever it wants to be. The math
gets ugly.
The sooner and tighter we can close the loop, the less the LC drifts.
On Tuesday, August 25, 2020 at 7:25:08 PM UTC-7, jla...@highlandsniptechnology.com wrote:
On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), \"John Miles, KE5FX\"
jmiles@gmail.com> wrote:
On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
....
It\'s a PLL, and lag slows down the loop dynamics.
I start an LC oscillator when I get a trigger, and use it to time out
delays. The ADC is clocked from an OCXO and observes the waveform of
the triggered LC oscillator, and I close a loop to lock the LC to the
XO. Actually, the LC frequency is whatever it wants to be. The math
gets ugly.
So, the LC is just an inaccurate copy of the XO?
The sooner and tighter we can close the loop, the less the LC drifts.
The LC has a high Q, I assume, and that means it has low phase noise, but
you\'re steering it, which means you aren\'t getting the Q advantage and
your phase noise includes artifacts due to corrections.
Maybe downmix the LC oscillator against a filtered PLL (as the local oscillator)
which gives a low-frequency error signal, easily measured. Any frequency/phase
comparison/correction will take time according to the frequency resolution,
though. Measure, and use the info for a correction afterwards, might be easier than
control at HF in realtime.
I\'m digitizing a capacitive linear ramp anyhow!
Your favourite supplier has a dual 800Mhz one:Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
On 25/08/2020 19:34, John Larkin wrote:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
Your favourite supplier has a dual 800Mhz one:
MAX105ECS+
Mouser have stock.
On Tue, 25 Aug 2020 18:42:22 -0700 (PDT), \"John Miles, KE5FX\"
jmiles@gmail.com> wrote:
On Tuesday, August 25, 2020 at 11:34:31 AM UTC-7, John Larkin wrote:
Does anybody know of one? I\'d like to digitize 6 bits or so, really
fast. Most fast ADCs take 3 or 4 clocks to process the data. Even 4
bits might work.
Classic \"flash\" ADCs were fast, but needed 2^N comparators.
What are you trying to do that can\'t wait a few clock cycles?
-- john, KE5FX
It\'s a PLL, and lag slows down the loop dynamics.
I start an LC oscillator when I get a trigger, and use it to time out
delays. The ADC is clocked from an OCXO and observes the waveform of
the triggered LC oscillator, and I close a loop to lock the LC to the
XO. Actually, the LC frequency is whatever it wants to be. The math
gets ugly.
The sooner and tighter we can close the loop, the less the LC drifts.
There\'s a DAC too, but they\'re fast.
I just found this:
https://www.analog.com/en/products/adv7125.html
Triple 8-bit DAC, 330 MHz, cheap.