Non-intrusive readback operation

P

Pepi

Guest
Hello,

I was wondering if anyone knows if it's possible to perform a "non-
intrusive" FPGA readback operation (specifically for a Xilinx Virtex
5). Looking through the datasheet, I can find all the information
required to DO a readback, but I can't seem find anything regarding
whether or not it's intrusive.

Thanks a lot.

Pepi
 
Pepi wrote:

I was wondering if anyone knows if it's possible to perform a "non-
intrusive" FPGA readback operation
Click to expand...
I could write HDL for the FPGA
that describes such an interface.

Simplest case would be a synchronous
output port and data_ready strobe.

For multiple read/write registers
a bus interface with read/write
data buses, an address bus and
control strobes are often used.

-- Mike Treseler
 
On Apr 23, 12:54 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Pepi wrote:
I was wondering if anyone knows if it's possible to perform a "non-
intrusive" FPGA readback operation

I could write HDL for the FPGA
that describes such an interface.

Simplest case would be a synchronous
output port and data_ready strobe.

For multiple read/write registers
a bus interface with read/write
data buses, an address bus and
control strobes are often used.

-- Mike Treseler
Click to expand...
Hi Mike,

I'm afraid I wasn't clear enough in the description of my problem.
When I referred to a "readback operation", I meant a readback on the
configuration data loaded into the FPGA in order to verify its
correctness and ensure that it hasn't been corrupted.

Sorry about that...heh. Thanks though.

Pepi
 
Isn't that the job of the CRC?

"Pepi" <sumeet.abrol@gmail.com> wrote in message
news:1177349932.962545.326610@y80g2000hsf.googlegroups.com...
On Apr 23, 12:54 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Pepi wrote:
I was wondering if anyone knows if it's possible to perform a "non-
intrusive" FPGA readback operation

I could write HDL for the FPGA
that describes such an interface.

Simplest case would be a synchronous
output port and data_ready strobe.

For multiple read/write registers
a bus interface with read/write
data buses, an address bus and
control strobes are often used.

-- Mike Treseler

Hi Mike,

I'm afraid I wasn't clear enough in the description of my problem.
When I referred to a "readback operation", I meant a readback on the
configuration data loaded into the FPGA in order to verify its
correctness and ensure that it hasn't been corrupted.

Sorry about that...heh. Thanks though.

Pepi
Click to expand...
 
Yes, I agree that it is...

....but here's the twist. I'm not simply looking for the status of the
configuration data upon configuration. For whatever reason (believe
me, even I wish I didn't know why), I need to check the configuration
data on a whim at some point in time AFTER the FPGA has trasferred to
User Mode.

Any insight would be greatly appreciated.

Thanks again,

Sumeet
 
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