A
andersod2
Guest
According to the verilog article on wikipedia, when a non-blocking
assignment is used, the action doesn't take place until the next clock
cycle (I'm guessing this applies to when the clock is in the
sensitivity list). I'm not sure I understand why this is the case, as
well as, why this is not the case for blocking assignment. In other
words, why is it not just a matter of how the gates are arranged in
blocking vs non-blocking, and why would the clock have anything to do
with that?
TIA-
assignment is used, the action doesn't take place until the next clock
cycle (I'm guessing this applies to when the clock is in the
sensitivity list). I'm not sure I understand why this is the case, as
well as, why this is not the case for blocking assignment. In other
words, why is it not just a matter of how the gates are arranged in
blocking vs non-blocking, and why would the clock have anything to do
with that?
TIA-