Noise modelling in transient simulation

C

Christian Auner

Guest
Hi!

I want to include models (eg VerilogA) that create a noisy signal during a
transient simulation run. I'm not sure how to approach this problem, I
guess that adding a block that has a random output will only cause
convergence problems. That's why I think that I somehow have to change the
output exactly once at certain intervalls.
Any ideas? Thank you in advance!

Chris.
 
I don't think it would necessarily cause convergence issues, but it probably
doesn't make sense to make it random at each timestep with variable
timesteps.

You could use the @(timer(...)) type approach. Take a look at rand_bit_stream
in ahdlLib as an example; this is generating a random bit output on a clocked
period.

Regards,

Andrew.


On Mon, 24 May 2004 19:36:56 +0200, Christian Auner <mca@nurfuerspam.de> wrote:

Hi!

I want to include models (eg VerilogA) that create a noisy signal during a
transient simulation run. I'm not sure how to approach this problem, I
guess that adding a block that has a random output will only cause
convergence problems. That's why I think that I somehow have to change the
output exactly once at certain intervalls.
Any ideas? Thank you in advance!

Chris.
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
 
Hi Chris,

I want to include models (eg VerilogA) that create a noisy signal during a
transient simulation run. I'm not sure how to approach this problem, I
guess that adding a block that has a random output will only cause
convergence problems. That's why I think that I somehow have to change the
output exactly once at certain intervalls.
If I want to do this, I use matlab (or octave) to generate the noise
that I want (so 1/f for instance) and then output the values to a file
as time/voltage (or time/current) pairs and then use the file with a
piece wise linear source (vpwlf or ipwlf).

http://glory.eee.nott.ac.uk/userguides/guides/cadence_waveform.pdf

Hope this helps,

Roger
 

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