Node instance

S

Sushma

Guest
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file. I am getting an
error node instance i_fsm1 instantiates undefined entity fsm1. What do
I need to do so it sees my fsm1.vhd file. I am new to Quartus. Please
help

i_fms1 : fsm1
port map(
mclk => mclk,
ext_swtrig => ext_swtrig,
ext_trig => ext_trig,
sw_trig => sw_trig,
th_trig => th_trig,
trig_gate => trig_gate,
th_gate => th_gate,
strig => strig,
t0 => open,
t1 => open,
swreset => swreset
);
 
After architecture, did you defined component fsm1???

2 solutions. Either define component fsm1 after architecture or change
i_fms1 : fsm1 to i_fsm1 : work.fsm1...
(Assuming your current library is work and fsm1 is a vhdl code.)

Regards,
JK
 
On May 23, 9:15 am, JK <krishna.januman...@gmail.com> wrote:
After architecture, did you defined component fsm1???

2 solutions. Either define component fsm1 after architecture or change
i_fms1 : fsm1 to i_fsm1 : work.fsm1...
(Assuming your current library is work and fsm1 is a vhdl code.)

Regards,
JK
Click to expand...
Sorry .... change i_fms1 : fsm1 to i_fsm1 : entity work.fsm1 port map
(...)

Regards,
JK
 
On May 23, 12:22 am, JK <krishna.januman...@gmail.com> wrote:
On May 23, 9:15 am, JK <krishna.januman...@gmail.com> wrote:

After architecture, did you defined component fsm1???

2 solutions. Either define component fsm1 after architecture or change
i_fms1 : fsm1 to i_fsm1 : work.fsm1...
(Assuming your current library is work and fsm1 is a vhdl code.)

Regards,
JK

Sorry .... change i_fms1 : fsm1 to i_fsm1 : entity work.fsm1 port map
(...)

Regards,
JK
Click to expand...
Hello JK:
Thanks foe the reply. I changed fsm1 to entity work.fsm1. I
also added a line library ieee,work; at the top of the VHDL file. fsm1
is a VHDL file. I saved that file in my current project folder.Is
there anything else I need to do? I am sure I am missing something. I
am getting an error design library work does not contain primary unit
fsm1.
 
Sushma wrote:
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file.
Click to expand...
If I were testing a design entity on quartus,
I would just put the source on the file list
as the top entity and run synthesis.
No need to instance it.

-- Mike Treseler
 
On May 23, 12:25 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Sushma wrote:
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file.

If I were testing a design entity on quartus,
I would just put the source on the file list
as the top entity and run synthesis.
No need to instance it.

-- Mike Treseler
Click to expand...
Mike:
Can you please explain it further? I am unable to follow you. I
appreciate your help

Thanks
Sushma
 
On May 23, 12:25 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Sushma wrote:
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file.

If I were testing a design entity on quartus,
I would just put the source on the file list
as the top entity and run synthesis.
No need to instance it.

-- Mike Treseler
Click to expand...
Mike:
Can you please explain it further? I am unable to follow you. I
appreciate your help

Thanks
Sushma
 
On May 23, 12:25 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Sushma wrote:
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file.

If I were testing a design entity on quartus,
I would just put the source on the file list
as the top entity and run synthesis.
No need to instance it.

-- Mike Treseler
Click to expand...
Mike:
Can you please explain it further? I am unable to follow you. I
appreciate your help

Thanks
Sushma
 
On May 23, 12:25 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Sushma wrote:
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file.

If I were testing a design entity on quartus,
I would just put the source on the file list
as the top entity and run synthesis.
No need to instance it.

-- Mike Treseler
Click to expand...
Mike:
Can you please explain it further? I am unable to follow you. I
appreciate your help

Thanks
Sushma
 
On May 23, 12:25 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Sushma wrote:
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file.

If I were testing a design entity on quartus,
I would just put the source on the file list
as the top entity and run synthesis.
No need to instance it.

-- Mike Treseler
Click to expand...
Mike:
Can you please explain it further? I am unable to follow you. I
appreciate your help

Thanks
Sushma
 
On May 23, 12:25 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
Sushma wrote:
I am coding a project using VHDL in quartus II. I wrote the code and
trying to instantiate my state machine from this file.

If I were testing a design entity on quartus,
I would just put the source on the file list
as the top entity and run synthesis.
No need to instance it.

-- Mike Treseler
Click to expand...
Mike:
Can you please explain it further? I am unable to follow you. I
appreciate your help

Thanks
Sushma
 
On May 23, 7:23 pm, Sushma <sushmasri...@gmail.com> wrote:
On May 23, 12:22 am, JK <krishna.januman...@gmail.com> wrote:





On May 23, 9:15 am, JK <krishna.januman...@gmail.com> wrote:

After architecture, did you defined component fsm1???

2 solutions. Either define component fsm1 after architecture or change
i_fms1 : fsm1 to i_fsm1 : work.fsm1...
(Assuming your current library is work and fsm1 is a vhdl code.)

Regards,
JK

Sorry .... change i_fms1 : fsm1 to i_fsm1 : entity work.fsm1 port map
(...)

Regards,
JK

Hello JK:
Thanks foe the reply. I changed fsm1 to entity work.fsm1. I
also added a line library ieee,work; at the top of the VHDL file. fsm1
is a VHDL file. I saved that file in my current project folder.Is
there anything else I need to do? I am sure I am missing something. I
am getting an error design library work does not contain primary unit
fsm1.- Hide quoted text -

- Show quoted text -
Click to expand...
It seems your work library dont have compiled fsm1 and in your design,
fsm1 is not getting compiled before your main program (from where you
are calling fsm1). Just see messages/warnings when you are compiling
the design.

Have you tried first solution? Adding component fsm1 after
architecture and port mapping it (as it is in your question).
Here also observe weather fsm1 is getting compiled before your main
program.

Regards,
JK
 
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