(no subject)

Often when I extract a Spectre netlist in Cadence I get a warning
that indicates I have a mismatch between the terminals in cellview
and the pin order on schematic or termOrder property on the CDF.

While it doesn't seem to cause a problem, what is this, and how do
I correct it or prevent it from happening?

Regards,

Barry
 
Hi,

This often happens if you already have a schematic and a symbol
view of your cell and you manually modify your terminals in the
schematic and then to have the correspondence also in your symbol.

If you do this manually which means not use the create cellview form
cellview command your component description format CDF for this cell
gets not updated and as a result you will see this warning.

So use the create cellview form cellview to update your symbol and the
the modify option or you have to update your CDF also manually according
to your terminal changes.

Bernd

Barry Bass wrote:
Often when I extract a Spectre netlist in Cadence I get a warning
that indicates I have a mismatch between the terminals in cellview
and the pin order on schematic or termOrder property on the CDF.

While it doesn't seem to cause a problem, what is this, and how do
I correct it or prevent it from happening?

Regards,

Barry
Click to expand...
 
Also happens when you copy (move) a cell to another library and (of
course by default)
or "add" a terminal, edit a pin name, dick with the terminal netlisting
order .. add code to change thi instance
name (the infamous poymophic device .... ) ....

the required CDF gets left behind ... another framework blunder .... but
you can "fix" it by doing a CDF copy ....

rant mode on ...

what a load of .$%^&* CDF is ..
Istill remember when netlisting/terminal info was visible as properties
on cells
..... (hint hint ) .. but then again I was around when the framework was
called SDA & I knew Jim.

oh well ..

rant mode off



YMMV -- Gerry

Bernd Fischer wrote:

Hi,

This often happens if you already have a schematic and a symbol
view of your cell and you manually modify your terminals in the
schematic and then to have the correspondence also in your symbol.

If you do this manually which means not use the create cellview form
cellview command your component description format CDF for this cell
gets not updated and as a result you will see this warning.

So use the create cellview form cellview to update your symbol and the
the modify option or you have to update your CDF also manually according
to your terminal changes.

Bernd

Barry Bass wrote:

Often when I extract a Spectre netlist in Cadence I get a warning
that indicates I have a mismatch between the terminals in cellview
and the pin order on schematic or termOrder property on the CDF.

While it doesn't seem to cause a problem, what is this, and how do
I correct it or prevent it from happening?

Regards,

Barry
Click to expand...
 
Barry:
There is an option you can set in IC5141 to update the termOrder
property when the symbol is checked and saved:
envSetVal("auCore.misc" "updateCDFtermOrder" 'boolean t)

In IC5033 it is:
envSetVal("asimenv.misc" "updateCDFtermOrder" 'boolean t)

The SKILL command to update the CDF simInfo section is:
artGenerateHierSymbolCDF(cv_dbid)

The artGenerateHierSymbolCDF function opens up a pop up box asking if
you want to overwrite the base CDF. You could instead update the
termOrder list as follows instead of using artGenerateHierSymbolCDF():

;***
cdf_dbid = cdfGetBaseCellCDF(cv_dbid~>cell)

;get and alphabatize terminal list
atoz_terminal_list = sort(cv_dbid~>terminals~>name nil)

;generate string list of simulators
simulator_list = cdf_dbid->simInfo->?
foreach(simulator simulator_list

if(get(cdf_dbid->simInfo simulator)->termOrder !=
atoz_terminal_list then

get(cdf_dbid->simInfo simulator)->termOrder = atoz_terminal_list
printf("[INFO] Updated %-9s simInfo termOrder to %L\n" simulator
atoz_terminal_list)
) ; if

) ; foreach
cdfSaveCDF(cdf_dbid)
;***

Note that veriloga has a section called viewInfo similar to termOrder
which can be updated with the following function:
ahdlUpdateViewInfo(cv_dbid~>libName ?cell cv_dbid~>cellName ?view
view)

I have a fundamental question that I can't get anyone at Cadence to
answer. Why does create cellview from cellview add the termOrder
property (it would netlist fine without it, correct)? All the
termOrder property does is create grief as it might not get updated
properly as terminals are added and deleted and create this mismatch
which causes confusion and wastes our time... What is the reason for
this property and what is the valid use case?
---
Erik



Duncan Barclay <dmlb@dmlb.org> wrote in message news:<4163331B.3080406@dmlb.org>...
Barry Bass wrote:

Often when I extract a Spectre netlist in Cadence I get a warning
that indicates I have a mismatch between the terminals in cellview
and the pin order on schematic or termOrder property on the CDF.

While it doesn't seem to cause a problem, what is this, and how do
I correct it or prevent it from happening?

Barry, as others have indicated this is when the symbol, schematic and
CDF get out of sync.

Most of the time, the Spectre default netlist order gets things right (I
cannot remember the details but it does something input/outputs,
outputs, inputs with each in alphabetical order). However, in the past
we've been really burnt by this with circuits that appear to be
connected correctly not simulating correctly for no reason. Until we
look at netlist and realise that the power supply is connected backwards...

The rule that I try and drum into people I work with is that if you see
this, disregard simulation results and regenerate the symbol+CDF. The
manual way is to rename a pin in the schematic, do a create cellview
from cellview, and then name it back again. This gets everything in sync
and has worked without fail since about IC4.4.3.

As I mentioned above, most of the time things are okay and you can
ignore this, but I never let sign off simulations have this error...

Duncan

Regards,

Barry
Click to expand...
 
erikwanta@starband.net (Erik Wanta) wrote in message news:<84018314.0410060123.44d30b7e@posting.google.com>...
Barry:
There is an option you can set in IC5141 to update the termOrder
property when the symbol is checked and saved:
envSetVal("auCore.misc" "updateCDFtermOrder" 'boolean t)

In IC5033 it is:
envSetVal("asimenv.misc" "updateCDFtermOrder" 'boolean t)

The SKILL command to update the CDF simInfo section is:
artGenerateHierSymbolCDF(cv_dbid)
Click to expand...
Dude, you rock! I was just looking for exactly that, thanks.

-Jay-
 
Erik,

Good question indeed.

You can supress the CDF generation when you do schematic CV to symbol. Just mess up with
schCvToCvTriggers->triggers
You can probably even define you own trigger that will delete the termOrder CDF.

If you try it, tell me if that has no nasty effect further in the flow. It would not be so surprising that some tool expects termOrder.

Erik Wanta wrote:
Barry:
There is an option you can set in IC5141 to update the termOrder
property when the symbol is checked and saved:
envSetVal("auCore.misc" "updateCDFtermOrder" 'boolean t)

In IC5033 it is:
envSetVal("asimenv.misc" "updateCDFtermOrder" 'boolean t)

The SKILL command to update the CDF simInfo section is:
artGenerateHierSymbolCDF(cv_dbid)

The artGenerateHierSymbolCDF function opens up a pop up box asking if
you want to overwrite the base CDF. You could instead update the
termOrder list as follows instead of using artGenerateHierSymbolCDF():

;***
cdf_dbid = cdfGetBaseCellCDF(cv_dbid~>cell)

;get and alphabatize terminal list
atoz_terminal_list = sort(cv_dbid~>terminals~>name nil)

;generate string list of simulators
simulator_list = cdf_dbid->simInfo->?
foreach(simulator simulator_list

if(get(cdf_dbid->simInfo simulator)->termOrder !=
atoz_terminal_list then

get(cdf_dbid->simInfo simulator)->termOrder = atoz_terminal_list
printf("[INFO] Updated %-9s simInfo termOrder to %L\n" simulator
atoz_terminal_list)
) ; if

) ; foreach
cdfSaveCDF(cdf_dbid)
;***

Note that veriloga has a section called viewInfo similar to termOrder
which can be updated with the following function:
ahdlUpdateViewInfo(cv_dbid~>libName ?cell cv_dbid~>cellName ?view
view)

I have a fundamental question that I can't get anyone at Cadence to
answer. Why does create cellview from cellview add the termOrder
property (it would netlist fine without it, correct)? All the
termOrder property does is create grief as it might not get updated
properly as terminals are added and deleted and create this mismatch
which causes confusion and wastes our time... What is the reason for
this property and what is the valid use case?
---
Erik



Duncan Barclay <dmlb@dmlb.org> wrote in message news:<4163331B.3080406@dmlb.org>...

Barry Bass wrote:


Often when I extract a Spectre netlist in Cadence I get a warning
that indicates I have a mismatch between the terminals in cellview
and the pin order on schematic or termOrder property on the CDF.

While it doesn't seem to cause a problem, what is this, and how do
I correct it or prevent it from happening?

Barry, as others have indicated this is when the symbol, schematic and
CDF get out of sync.

Most of the time, the Spectre default netlist order gets things right (I
cannot remember the details but it does something input/outputs,
outputs, inputs with each in alphabetical order). However, in the past
we've been really burnt by this with circuits that appear to be
connected correctly not simulating correctly for no reason. Until we
look at netlist and realise that the power supply is connected backwards...

The rule that I try and drum into people I work with is that if you see
this, disregard simulation results and regenerate the symbol+CDF. The
manual way is to rename a pin in the schematic, do a create cellview
from cellview, and then name it back again. This gets everything in sync
and has worked without fail since about IC4.4.3.

As I mentioned above, most of the time things are okay and you can
ignore this, but I never let sign off simulations have this error...

Duncan


Regards,

Barry
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top