J
Jerry Johns
Guest
Hello folks,
I have a top level design for a risc cpu, and i find
that all though all my pipelined modules run off a single clk signal,
the top level design during synthesis in Xilinx, does not show timing
information..it always says, "No clock signals found in design" and "No
path found" subsequently after..i want to point Xilinx to the fact that
there is a clk path for which timing info should be displayed so that i
can later optimize my design accordingly..
anyone have a clue how to do this? i posted before..but i dont think it
showed up
Jerry
I have a top level design for a risc cpu, and i find
that all though all my pipelined modules run off a single clk signal,
the top level design during synthesis in Xilinx, does not show timing
information..it always says, "No clock signals found in design" and "No
path found" subsequently after..i want to point Xilinx to the fact that
there is a clk path for which timing info should be displayed so that i
can later optimize my design accordingly..
anyone have a clue how to do this? i posted before..but i dont think it
showed up
Jerry