No clock signals found in design

J

Jerry Johns

Guest
I have a problem with the following Forward unit design in my RISC CPU.
It synthesizes fine, but Xilinx is unable to find the right clock
signal to optimize on

-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 1 |
N166(_n0012<2>277:O) | NONE(*)(stallc) | 1 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically
buffered by XST with BUFG/BUFR resources. Please use the buffer_type
constraint in order


How do i correct this and tell it to point to clk as the one to display
clk info on?
Here's my CODE:

-------------------------------------------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:27:26 08/17/06
// Design Name:
// Module Name: fwdunit
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fwdunit(
clk,
rst,
dec_op1, //op1 from decoder
dec_op2, //op2 from decoder
dec_op3, //op3 (during Stores)
ex_op2, //op2 from EX unit
load_exop, //ack that EXE unit has a LDD operation to op2
destination
force_wbop2, //force fwd unit to use WB results as base for ALU (NOTE
if STALL sig is used for other reasons than forwarding, then this is
not pertinent)
wb_op2,
gpr_d1,
gpr_d2,
gpr_d3,
ex_d2,
wb_d2,
d1,
d2,
d3,
stall
);

input clk;
input rst;
input [4:0] dec_op1;
input [4:0] dec_op2;
input [4:0] dec_op3;
input force_wbop2;

input [4:0] ex_op2;
input [4:0] wb_op2;
input load_exop;

input [7:0] gpr_d1;
input [7:0] gpr_d2;
input [7:0] gpr_d3;

input [7:0] ex_d2;
input [7:0] wb_d2;

output [7:0] d1;
wire [7:0] d1w;
output [7:0] d2;
output [7:0] d3;
output stall;

wire comp1, comp2, comp3, comp4;
reg stallc;
reg stall2c;

assign d1w = (dec_op1==ex_op2) ? ex_d2 : (dec_op1==wb_op2) ? wb_d2 :
gpr_d1;
assign d1 = (force_wbop2) ? wb_d2 : d1w;
assign d2 = (dec_op2==ex_op2) ? ex_d2 : (dec_op2==wb_op2) ? wb_d2 :
gpr_d2;
assign d3 = (dec_op3==ex_op2) ? ex_d2 : (dec_op3==wb_op2) ? wb_d2 :
gpr_d3;

assign stall = stallc & stall2c;

//synthesis attribute clock_signal of clk is true;
//synthesis attribute clock_signal of load_exop is false;

always @ (load_exop) begin
if (load_exop == 1'b1) begin
if ((dec_op1 == ex_op2) & (load_exop))
stallc <= 1;
end
else begin
stallc <= 0;
end

end

always @ (posedge clk) begin
if (rst) begin
stall2c <= 1'b1;
end

if (stallc == 1'b1)
stall2c <= 1'b0;
else
stall2c <= 1'b1;
end



endmodule
 
just for clarification as to what this module does..
i have a RISC, with such a order: IF_fetch, decode, alu, mem_wb

load_exop is a sig from ALU telling me a load operation is underway in
ALU,
and dec_op1 is op1 from decode block, and ex_op2 is op2 from ALU
block...to forward data in RISC, ex_op2 and dec_op1 have to equal each
other..but in this case, a load is underway so a stall is unavoidable
so i have to use combinational logic to generate a stall sig so that by
the next clk edge, both these blocks will recognize stall sig and
stalll

however, i also need the benefit of having the stall sig deasserted at
the next clk edge, hence why i have stall2c being used as a AND block
input to deassert stall sig on next edge

using a combination of stallc, and stall2c, i can satisfy these
requirements.
 
My own suggestions are in the altered code below:

Jerry Johns wrote:
I have a problem with the following Forward unit design in my RISC CPU.
It synthesizes fine, but Xilinx is unable to find the right clock
signal to optimize on

-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 1 |
N166(_n0012<2>277:O) | NONE(*)(stallc) | 1 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically
buffered by XST with BUFG/BUFR resources. Please use the buffer_type
constraint in order


How do i correct this and tell it to point to clk as the one to display
clk info on?
Here's my CODE:

-------------------------------------------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:27:26 08/17/06
// Design Name:
// Module Name: fwdunit
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fwdunit(
clk,
rst,
dec_op1, //op1 from decoder
dec_op2, //op2 from decoder
dec_op3, //op3 (during Stores)
ex_op2, //op2 from EX unit
load_exop, //ack that EXE unit has a LDD operation to op2
destination
force_wbop2, //force fwd unit to use WB results as base for ALU (NOTE
if STALL sig is used for other reasons than forwarding, then this is
not pertinent)
wb_op2,
gpr_d1,
gpr_d2,
gpr_d3,
ex_d2,
wb_d2,
d1,
d2,
d3,
stall
);

input clk;
input rst;
input [4:0] dec_op1;
input [4:0] dec_op2;
input [4:0] dec_op3;
input force_wbop2;

input [4:0] ex_op2;
input [4:0] wb_op2;
input load_exop;

input [7:0] gpr_d1;
input [7:0] gpr_d2;
input [7:0] gpr_d3;

input [7:0] ex_d2;
input [7:0] wb_d2;

output [7:0] d1;
wire [7:0] d1w;
output [7:0] d2;
output [7:0] d3;
output stall;

wire comp1, comp2, comp3, comp4;
reg stallc;
reg stall2c;

assign d1w = (dec_op1==ex_op2) ? ex_d2 : (dec_op1==wb_op2) ? wb_d2 :
gpr_d1;
assign d1 = (force_wbop2) ? wb_d2 : d1w;
assign d2 = (dec_op2==ex_op2) ? ex_d2 : (dec_op2==wb_op2) ? wb_d2 :
gpr_d2;
assign d3 = (dec_op3==ex_op2) ? ex_d2 : (dec_op3==wb_op2) ? wb_d2 :
gpr_d3;

assign stall = stallc & stall2c;

//synthesis attribute clock_signal of clk is true;
//synthesis attribute clock_signal of load_exop is false;
Click to expand...
always @* // <-- if you want the result to be combinatorial, give it
*every* input
if( load_exop & dec_op1==ex_op2 )
stallc <= 1;
else // You used to have a latch structure
stallc <= 0; // If !load_exop, the value would have held

// better as: wire stallc = load_exop & dec_op1==exop2;

always @ (posedge clk)
if( rst )
stall2c <= 1'b1; // reset didn't do anything before because
else if( stallc ) // <-- you forgot the else
stall2c <= 1'b0;
else
stall2c <= 1'b1;

endmodule


When you use always blocks for combinatorial logic, all the conditions
in an if/else block must be included or the logic will be a latch. As
you specified it, the logic was explicitly a latch with the load_exop
clock signal. If you can describe a combinatorial function clearly and
succinctly in a single assignment, I would always recommend it over the
always block.

- John_H
 
thanks a lot John, thats quite an effective optimization u stated
there; though it fixed it, i still dont get clk timing information
during synthesis "No clock signals found in design"..i've even put in a
//sythesis attribute clock_signal of clk is true;

i have a follow up question : in my risc, as i mentioned before, i have
fetch,decode,fwd_unit,gpr,alu and mem_wb.

when i synthesized my proc_top, my timing comes back at 200Mhz, but the
path runs through fetch and decode (its telling me thats the longest
path)...how can i trust that knowing thats the longest delay? i tried
using the timing analyzer to find delay for a custom path from a sig in
fetch to a sig in mem_wb but i couldn't get any results
 
Jerry Johns wrote:
thanks a lot John, thats quite an effective optimization u stated
there; though it fixed it, i still dont get clk timing information
during synthesis "No clock signals found in design"..i've even put in a
//sythesis attribute clock_signal of clk is true;

i have a follow up question : in my risc, as i mentioned before, i have
fetch,decode,fwd_unit,gpr,alu and mem_wb.

when i synthesized my proc_top, my timing comes back at 200Mhz, but the
path runs through fetch and decode (its telling me thats the longest
path)...how can i trust that knowing thats the longest delay? i tried
using the timing analyzer to find delay for a custom path from a sig in
fetch to a sig in mem_wb but i couldn't get any results
Click to expand...
Can your synthesizer show you the critical path? I like SynplifyPro's
HDL Analyst, myself.

Do you have only one master frequency specified in your design?

Does your Timing Analyzer allow you to use auto-generated timing
constraints? If so, try those for a "complete" report.

If you mention your specific tools and target silicon, perhaps others
can comment on the timing analyzer and expected performance.
 
Hey,
Yup i'm running off a master frequency clk - the PAR and
synthesis both show timing information, and the critical path; the
timing analyzer from xiilnx shows a more in depth information on the
delays; the analyzer also has an auto constraint option which is useful

however, i dont get to see this information pictorially :( all this
shows up as info about net to net delays, and the net names are
convulated and auto created by xilinx

i was wondering if anyone knew of a way to see this info in pictorial
way? i also have modelSIM installed
 
also, i was wondering if i put a DCM in the input clk sig and use
deskewing, will that help my overall synthesizable clk frequency? the
CLK0 will be bufged before putting back to the clk_fb port

do i just need one dcm, or should i put multiple depending on location
of the input clk to the variuos modules (find the highest skewed clk
trace, and add a dcm there)
 
Hi Jerry,
Check whether the register still exist after synthesis. It is a
constant value and may get optimized after synthesis. You may want to
check the variation to disable constant propagation before synthesis. I
am not sure there is such feature using ISE or not.

always @ (posedge clk)
if( rst )
stall2c <= 1'b1; // reset didn't do anything before because
else if( stallc ) // <-- you forgot the else
stall2c <= 1'b0;
else
stall2c <= 1'b1;


endmodule



Best regards,
ABC

Jerry Johns wrote:
I have a problem with the following Forward unit design in my RISC CPU.
It synthesizes fine, but Xilinx is unable to find the right clock
signal to optimize on

-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 1 |
N166(_n0012<2>277:O) | NONE(*)(stallc) | 1 |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s)
generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically
buffered by XST with BUFG/BUFR resources. Please use the buffer_type
constraint in order


How do i correct this and tell it to point to clk as the one to display
clk info on?
Here's my CODE:

-------------------------------------------------------------------------------------------------------------------------------------

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:27:26 08/17/06
// Design Name:
// Module Name: fwdunit
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fwdunit(
clk,
rst,
dec_op1, //op1 from decoder
dec_op2, //op2 from decoder
dec_op3, //op3 (during Stores)
ex_op2, //op2 from EX unit
load_exop, //ack that EXE unit has a LDD operation to op2
destination
force_wbop2, //force fwd unit to use WB results as base for ALU (NOTE
if STALL sig is used for other reasons than forwarding, then this is
not pertinent)
wb_op2,
gpr_d1,
gpr_d2,
gpr_d3,
ex_d2,
wb_d2,
d1,
d2,
d3,
stall
);

input clk;
input rst;
input [4:0] dec_op1;
input [4:0] dec_op2;
input [4:0] dec_op3;
input force_wbop2;

input [4:0] ex_op2;
input [4:0] wb_op2;
input load_exop;

input [7:0] gpr_d1;
input [7:0] gpr_d2;
input [7:0] gpr_d3;

input [7:0] ex_d2;
input [7:0] wb_d2;

output [7:0] d1;
wire [7:0] d1w;
output [7:0] d2;
output [7:0] d3;
output stall;

wire comp1, comp2, comp3, comp4;
reg stallc;
reg stall2c;

assign d1w = (dec_op1==ex_op2) ? ex_d2 : (dec_op1==wb_op2) ? wb_d2 :
gpr_d1;
assign d1 = (force_wbop2) ? wb_d2 : d1w;
assign d2 = (dec_op2==ex_op2) ? ex_d2 : (dec_op2==wb_op2) ? wb_d2 :
gpr_d2;
assign d3 = (dec_op3==ex_op2) ? ex_d2 : (dec_op3==wb_op2) ? wb_d2 :
gpr_d3;

assign stall = stallc & stall2c;

//synthesis attribute clock_signal of clk is true;
//synthesis attribute clock_signal of load_exop is false;

always @ (load_exop) begin
if (load_exop == 1'b1) begin
if ((dec_op1 == ex_op2) & (load_exop))
stallc <= 1;
end
else begin
stallc <= 0;
end

end

always @ (posedge clk) begin
if (rst) begin
stall2c <= 1'b1;
end

if (stallc == 1'b1)
stall2c <= 1'b0;
else
stall2c <= 1'b1;
end



endmodule
Click to expand...
 
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