NIOS Board Stratix Edition - FPGA won't configure

[vadim]

I am having problem with my NIOS Stratix Board. I am not
able to download just my own, simple, compiled VHDL code onto
the Stratix FPGA. The device is EP1S10F780C6ES.
After JTAG (ByteBlaster) download finishes, the board resets
and MAX configuration-device loads Stratix with the default
configuration stored in the on-board FLASH memory (which is a
NIOS based server thingy). I tried loading to the FLASH and that failed too.

Any ideas ?

 

[Subroto Datta]

Vadim, make sure that you have the Unused Pins for your Quartus project set
to be Inputs Tristated. You can do this as follows after the project is
opened in Quartus:

1. Click on Assign Device
2. Click on the Device and Pin Options Button
3. Click on the Unused Pins Tab.
4. This should be the first Radio button.

Hope this helps.

- Subroto Datta
Altera Corp.

 

[Jesse Kempa]

"Subroto Datta" <sdatta@altera.com> wrote in message news:<n4zqc.524$1O4.119@newssvr15.news.prodigy.com>...

Vadim, make sure that you have the Unused Pins for your Quartus project set
to be Inputs Tristated. You can do this as follows after the project is
opened in Quartus:

1. Click on Assign Device
2. Click on the Device and Pin Options Button
3. Click on the Unused Pins Tab.
4. This should be the first Radio button.

Hope this helps.

- Subroto Datta
Altera Corp.

Just to elaborate on why this is:

A feature of the Nios development boards is to demonstrate remote
reconfiguration. This is done via an FPGA I/O which is connected to
the MAX CPLD on the board. The MAX CPLD is programmed to re-configure
the FPGA when the signal is driven low (in this way, the FPGA can send
a signal telling the MAX chip to reconfigure itself). For reference
designs that include this pin and leave it high, or tri-stated, there
is no issue. However, a user design must either drive this pin high
manually, tri-state the pin manually, or leave the pin un-assigned and
tri-state the unused outputs (as Subroto's instructions indicate).

Regards,

Jesse Kempa
Altera Corp.
jkempa at altera dot com

 

[Petter Gustad]

kempaj@yahoo.com (Jesse Kempa) writes:

"Subroto Datta" <sdatta@altera.com> wrote in message news:<n4zqc.524$1O4.119@newssvr15.news.prodigy.com>...
Vadim, make sure that you have the Unused Pins for your Quartus project set
to be Inputs Tristated. You can do this as follows after the project is
opened in Quartus:

1. Click on Assign Device
2. Click on the Device and Pin Options Button
3. Click on the Unused Pins Tab.
4. This should be the first Radio button.

Hope this helps.

- Subroto Datta
Altera Corp.


Just to elaborate on why this is:

A feature of the Nios development boards is to demonstrate remote
reconfiguration. This is done via an FPGA I/O which is connected to
the MAX CPLD on the board. The MAX CPLD is programmed to re-configure
the FPGA when the signal is driven low (in this way, the FPGA can send
a signal telling the MAX chip to reconfigure itself). For reference
designs that include this pin and leave it high, or tri-stated, there
is no issue. However, a user design must either drive this pin high
manually, tri-state the pin manually, or leave the pin un-assigned and

I informed Vadim about reconfigure issue a few weeks ago in:

http://groups.google.com/groups?safe=images&ie=UTF-8&as_ugroup=sci.electronics.cad&as_umsgid=m3brlbcge1.fsf@scimul.dolphinics.no&lr=&hl=en


Maybe there's another problem?

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Subroto Datta]

Vadim acknowledged that setting the Unused Pins to be Iputs tristated solved
his problem.

- Subroto

"Petter Gustad" <newsmailcomp6@gustad.com> wrote in message
news:87isescgh0.fsf@filestore.home.gustad.com...

Maybe there's another problem?

Petter

 

[vadim]

I was fully aware that the MAX CPLD was programming the Stratix
device. We tried
to find the pin that is connected to the MAX CPLD and program it to be
tied to VCC (reconfig_req_n). This failed.
I was not aware there was a software setting inside Quartus to
Tri-State unused pins, which only found through this newsgroup (thing
like this should appear
on the front pages of the NIOS Board manual).

Generally, from working and learning Altera devices and software a
pattern seems to emerge - bad and ambiguous documentation. Huge and
wordy documents
that don't state the "beef" but tend to repeat things without much
elaboration.
This reminded me of learning Cadence software...

Thanks to Subroto and this forum the issue got solved now... (new ones
sure will come)

 

[Jesse Kempa]

vbishtei@hotmail.com (vadim) wrote in message news:<2a613f5d.0405231856.56b8c5ae@posting.google.com>...

I was fully aware that the MAX CPLD was programming the Stratix
device. We tried
to find the pin that is connected to the MAX CPLD and program it to be
tied to VCC (reconfig_req_n). This failed.
I was not aware there was a software setting inside Quartus to
Tri-State unused pins, which only found through this newsgroup (thing
like this should appear
on the front pages of the NIOS Board manual).

Generally, from working and learning Altera devices and software a
pattern seems to emerge - bad and ambiguous documentation. Huge and
wordy documents
that don't state the "beef" but tend to repeat things without much
elaboration.
This reminded me of learning Cadence software...

Hi Vadim,

I'm sorry that this problem caused you any trouble. With regards to
documentation, I think a lot of people feel the same way. The
unfortunate thing is that some readers need a lot of hand-holding when
getting started with a new tool, while some prefer the 'beef' as you
mention (I personally prefer the no-nonsense brief approach myself). I
think an ideal solution would be to have the verbose, and then
ultra-brief versions of select documents. This is, of course, very
difficult when shipping a product as the documentation tends to
require a completed product from the engineering standpoint and it's a
real rush to get all the docs done correctly when the product is
nearly ready to go.

Anyways, about this issue specifically: There is now a warning that is
called out of regular text (i.e., not just a paragraph) in the Nios II
HW development tutorial that tells the reader to change this setting
before starting Quartus compilation. The revised tutorial is up on our
web site and will ship on the Nios II CDs shortly.

Jesse Kempa
Altera Corp.
jkempa at altera dot com