Nios 2 Cyclone II board problem with simple logic

[magic]

I have the Nios 2 board with cyclone II like this:
http://www.altera.com/products/devkits/altera/kit-nios-2c35.html

My problem is that I can't implement very simple program on the fpga.
On the beginning I want use switches and leds to view that my program
is running. When I plug in the power adapter to the board, the led
factory is on( Is this mode I red in the documentation is running the
NIOS 2 with simple program) . When I program fpga via USB Blaster for
a one second led User is on but after that it returns to the factory
mode and led factory is on. I don't know how to program this board
with simple logic program. Can anyone explain me what am I doing wrong?

 

[Nial Stewart]

When I program fpga via USB Blaster for
a one second led User is on but after that it returns to the factory
mode and led factory is on. I don't know how to program this board
with simple logic program. Can anyone explain me what am I doing wrong?

From memory one of the FPGA pins is 'reset_n' (or reset) into the CPLD that controls
configuration.

If this isn't held at the right polarity the image will be immediately reset.

Have a look at the example designs provided on the Altera web site.


Nial.

 

[magic]

On 2 Lis, 11:53, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:

 When I program fpga via USB Blaster for
a one second led User is on but after that it returns to the factory
mode and led factory is on. I don't know how to program this board
with simple logic program. Can anyone explain me what am I doing wrong?

From memory one of the FPGA pins is 'reset_n' (or reset) into the CPLD that controls
configuration.

If this isn't held at the right polarity the image will be immediately reset.

Have a look at the example designs provided on the Altera web site.

Nial.

On the Altera Web are only the NIOS examples. They don't say how
program FPGA like CPLD. Still I don't see this

 

[Nial Stewart]

On the Altera Web are only the NIOS examples. They don't say how
program FPGA like CPLD. Still I don't see this

The CPLD is a separate IC on the board that controls programming the FPGA,
you have to let this know the FPGA is programmed properly.

There is an output from the FPGA to this device, actually I think it's called
'reconfig_n', which lets the CPLD know the FPGA is programmed with a valid
image.

I'm not doing the donkey work for you, look at the board schematics or
an example FPGA design to see what I'm talking about.


Nial.

 

[H. Peter Anvin]

On 11/02/2010 10:00 AM, Nial Stewart wrote:

On the Altera Web are only the NIOS examples. They don't say how
program FPGA like CPLD. Still I don't see this


The CPLD is a separate IC on the board that controls programming the FPGA,
you have to let this know the FPGA is programmed properly.

There is an output from the FPGA to this device, actually I think it's called
'reconfig_n', which lets the CPLD know the FPGA is programmed with a valid
image.

I'm not doing the donkey work for you, look at the board schematics or
an example FPGA design to see what I'm talking about.

A good hint, though, is to make sure you know what unassigned pins are
set to. I believe the default in current versions of Quartus II is "as
output driving ground", which is probably a bad choice. I suggest "as
input with weak pullup" instead.

-hpa

 

[magic]

On 2 Lis, 19:15, "H. Peter Anvin" <h...@zytor.com> wrote:

A good hint, though, is to make sure you know what unassigned pins are
set to.  I believe the default in current versions of Quartus II is "as
output driving ground", which is probably a bad choice.  I suggest "as
input with weak pullup" instead.

Yes this is it. Now FPGA don't ground unassinged pins and in this way
configure CPLD MAX configuration circuit.
Thank You so much.

 

[Nial Stewart]

Yes this is it. Now FPGA don't ground unassinged pins and in this way
configure CPLD MAX configuration circuit.
Thank You so much.

OK, but if that is the fix you should check and drive that pin inactive
instead of allowing it to float (it might be tied inactive on the board,
I can't remember).



Nial.

 

[H. Peter Anvin]

On 11/03/2010 06:22 AM, Nial Stewart wrote:

Yes this is it. Now FPGA don't ground unassinged pins and in this way
configure CPLD MAX configuration circuit.
Thank You so much.

OK, but if that is the fix you should check and drive that pin inactive
instead of allowing it to float (it might be tied inactive on the board,
I can't remember).

It won't float with the weak pull-up, although actively driving it to
VCC is better for noise.

-hpa