newbies and quartus

[PATRICE]

Hello
Is it possible of simulating variables in quartus2 ?
I copy/paste a simple example in quartus, it compiles, simulates
the signals (i think signals are the nodes in quartus terminology???)
but cant get the variables values.
Maybe it is not possible ??? it is quartus web edition !

thanks all

 

[Mike Treseler]

PATRICE <patrice.ulrich@evc.net> wrote in message news:<40CDD107.E7C1988F@evc.net>...

Is it possible of simulating variables in quartus2 ?

Quartus does not support vhdl simulation.
Consider modelsim or sonata for that.
Quartus does support synthesis of code using variables.

I copy/paste a simple example in quartus, it compiles, simulates
the signals (i think signals are the nodes in quartus terminology???)

Signals are the ports and wires of any vhdl design.

but cant get the variables values.

A vhdl simulator can do this, but consider
first looking at the signals that are being
driven with values from variables.

-- Mike Treseler

 

[Ken Smith]

In article <865ab498.0406141359.7ce8e222@posting.google.com>,
Mike Treseler <mike_treseler@comcast.net> wrote:

PATRICE <patrice.ulrich@evc.net> wrote in message
news:<40CDD107.E7C1988F@evc.net>...

Is it possible of simulating variables in quartus2 ?

Quartus does not support vhdl simulation.

Quartus does have a simulator in it. Chances are this is the scope of his
question.

Quartus does support synthesis of code using variables.

In the synthesis result a variable is often optimized out of existance.
This also applies to signals. This could explain why he can't see them.

You can always force the issue buy bringing the signal out to a device
pin. In that case the optimizer can't remove it.

[... NODE ...]

The term "node" is often used to refer to a physical point such as the
output of a macro cell in the chip. As such the term can get confused
with "signal" which is how VHDL refers to something that could end up as a
node.
--
--
kensmith@rahul.net forging knowledge